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/titanic_41/usr/src/lib/libc/capabilities/sun4v/common/
H A Dmemset.s67 #include <sys/asi.h>
106 mov ASI_BLK_INIT_ST_QUAD_LDD_P, %asi
135 stxa %o1, [%o5+0x0]%asi
136 stxa %o1, [%o5+0x40]%asi
137 stxa %o1, [%o5+0x80]%asi
138 stxa %o1, [%o5+0xc0]%asi
140 stxa %o1, [%o5+0x8]%asi
141 stxa %o1, [%o5+0x10]%asi
142 stxa %o1, [%o5+0x18]%asi
143 stxa %o1, [%o5+0x20]%asi
[all …]
H A Dmemcpy.s160 #include <sys/asi.h>
353 mov %asi,%o4 ! save %asi
358 mov ASI_BLK_P, %asi ! setup %asi for block load/store
397 ldda [%o1]%asi,%d16 ! block load
405 stda %d0,[%o0]%asi
411 ldda [%o1+64]%asi,%d16
420 stda %d0,[%o0]%asi
443 ldda [%o1]%asi,%d16 ! block load
450 stda %d0,[%o0]%asi
457 ldda [%o1+64]%asi,%d16
[all …]
/titanic_41/usr/src/uts/sun4u/ml/
H A Dmach_copy.s35 #include <sys/asi.h>
82 wr %g0, ASI_USER, %asi
96 wr %g0, ASI_P, %asi
114 ! Undo asi register setting. Just set it to be the
117 wr %g0, ASI_P, %asi
173 wr %g0, ASI_P, %asi
225 stba %g0, [%o0]%asi
238 sta %g0, [%o0]%asi
246 stxa %g0, [%o0]%asi
270 rd %asi, %o3
[all …]
H A Dmach_xc.s79 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
81 stha %g6, [%g4 + TRAP_ENT_TL]%asi
83 stha %g6, [%g4 + TRAP_ENT_TT]%asi
84 stna %o3, [%g4 + TRAP_ENT_TR]%asi ! pc of the TL>0 handler
86 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
88 stxa %g6, [%g4 + TRAP_ENT_TSTATE]%asi
89 stna %sp, [%g4 + TRAP_ENT_SP]%asi
90 stna %o1, [%g4 + TRAP_ENT_F1]%asi ! arg 1
91 stna %o2, [%g4 + TRAP_ENT_F2]%asi ! arg 2
92 stna %g0, [%g4 + TRAP_ENT_F3]%asi
[all …]
H A Dmach_interrupt.s132 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
134 stha %g6, [%g4 + TRAP_ENT_TL]%asi
136 stha %g6, [%g4 + TRAP_ENT_TT]%asi
138 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
140 stxa %g6, [%g4 + TRAP_ENT_TSTATE]%asi
141 stna %sp, [%g4 + TRAP_ENT_SP]%asi
142 stna %g5, [%g4 + TRAP_ENT_TR]%asi ! pc of the TL>0 handler
143 stxa %g1, [%g4 + TRAP_ENT_F1]%asi
144 stxa %g2, [%g4 + TRAP_ENT_F3]%asi
145 stxa %g0, [%g4 + TRAP_ENT_F2]%asi
[all …]
H A Dtrap_table.s331 * wide address space via the designated asi. It is used to spill
369 * wide address space via the designated asi. It is used to spill
376 mov asi_num, %asi ;\
378 sta %l0, [%sp + 0]%asi ;\
379 sta %l1, [%sp + 4]%asi ;\
380 sta %l2, [%sp + 8]%asi ;\
381 sta %l3, [%sp + 12]%asi ;\
382 sta %l4, [%sp + 16]%asi ;\
383 sta %l5, [%sp + 20]%asi ;\
384 sta %l6, [%sp + 24]%asi ;\
[all …]
/titanic_41/usr/src/uts/sun4u/sys/
H A Dtraptrace.h101 uchar_t asi; /* cache for real asi */ member
142 #define TRAPTR_ASIBUF 28 /* cache of current asi */
146 #define TRAPTR_ASI ASI_MEM /* ASI to use for TRAPTR access */
174 * NOTE: this caches and resets %asi
190 rd %asi, ptr; \
203 wr %g0, TRAPTR_ASI, %asi; \
211 * (we also restore the asi register)
219 wr %g0, scr1, %asi; \
238 stha scr1, [addr + TRAP_ENT_TL]%asi
244 stha tl, [addr + TRAP_ENT_TL]%asi
[all …]
H A Dcheetahasm.h90 stxa scr3, [datap + CH_DC_IDX]%asi; /* store index */ \
91 stxa scr1, [datap + CH_DC_TAG]%asi; /* store tag */ \
95 stxa scr1, [datap + CH_DC_UTAG]%asi; \
97 stxa scr1, [datap + CH_DC_SNTAG]%asi; \
104 stxa scr1, [datap]%asi; \
123 stba scr1, [datap]%asi; \
186 stxa scr3, [datap + CH_IC_IDX]%asi; /* store index */ \
187 stxa scr1, [datap + CH_IC_PATAG]%asi; /* store pa tag */ \
191 stxa scr1, [datap + CH_IC_UTAG]%asi; \
194 stxa scr1, [datap + CH_IC_UPPER]%asi; \
[all …]
/titanic_41/usr/src/uts/sun4v/sys/
H A Dtraptrace.h146 uchar_t asi; /* cache for real asi */ member
194 #define TRAPTR_ASIBUF 28 /* cache of current asi */
203 #define TRAPTR_ASI ASI_MEM /* ASI to use for TRAPTR access */
231 * NOTE: this caches and resets %asi
247 rd %asi, ptr; \
260 wr %g0, TRAPTR_ASI, %asi; \
268 * (we also restore the asi register)
276 wr %g0, scr1, %asi; \
295 stba scr1, [addr + TRAP_ENT_TL]%asi; \
297 stba scr1, [addr + TRAP_ENT_GL]%asi
[all …]
/titanic_41/usr/src/uts/sun4v/ml/
H A Dmach_xc.s81 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
83 stha %g6, [%g4 + TRAP_ENT_TL]%asi
85 stha %g6, [%g4 + TRAP_ENT_TT]%asi
86 stna %o3, [%g4 + TRAP_ENT_TR]%asi ! pc of the TL>0 handler
88 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
90 stxa %g6, [%g4 + TRAP_ENT_TSTATE]%asi
91 stna %sp, [%g4 + TRAP_ENT_SP]%asi
92 stna %o1, [%g4 + TRAP_ENT_F1]%asi ! arg 1
93 stna %o2, [%g4 + TRAP_ENT_F2]%asi ! arg 2
94 stna %g0, [%g4 + TRAP_ENT_F3]%asi
[all …]
H A Dmach_locore.s670 * from a 32/64-bit * wide address space via the designated asi.
675 mov asi_num, %asi ;\
680 lda [%sp + 0]%asi, %l0 ;\
681 lda [%sp + 4]%asi, %l1 ;\
682 lda [%sp + 8]%asi, %l2 ;\
683 lda [%sp + 12]%asi, %l3 ;\
684 lda [%sp + 16]%asi, %l4 ;\
685 lda [%sp + 20]%asi, %l5 ;\
686 lda [%sp + 24]%asi, %l6 ;\
687 lda [%sp + 28]%asi, %l7 ;\
[all …]
H A Dwbuf.s109 mov ASI_MEM, %asi
110 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
111 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
112 stna %sp, [%g6 + MPCB_SPBUF]%asi
115 sta %g5, [%g6 + MPCB_WBCNT]%asi
165 mov ASI_MEM, %asi
166 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
167 lda [%g6 + MPCB_WBCNT]%asi, %g5
169 sta %g7, [%g6 + MPCB_WBCNT]%asi
175 stna %sp, [%g7 + MPCB_SPBUF]%asi
[all …]
/titanic_41/usr/src/common/crypto/md5/sparc/sun4v/
H A Dbyteswap.il52 wr %g0, %o0, %asi
56 rd %asi, %o0
60 lduwa [%o0]%asi, %o0
64 lduwa [%o0 + 4]%asi, %o0
68 lduwa [%o0 + 8]%asi, %o0
72 lduwa [%o0 + 12]%asi, %o0
76 lduwa [%o0 + 16]%asi, %o0
80 lduwa [%o0 + 20]%asi, %o0
84 lduwa [%o0 + 24]%asi, %o0
88 lduwa [%o0 + 28]%asi, %o0
[all …]
/titanic_41/usr/src/uts/sun4v/cpu/
H A Dniagara_copy.s32 #include <sys/asi.h>
2184 mov ASI_BLK_INIT_ST_QUAD_LDD_P, %asi
2201 ldda [%i1+0x0]%asi, %l2
2203 ldda [%i1+0x10]%asi, %l4
2206 stxa %l3, [%i0+0x0]%asi
2207 stxa %l4, [%i0+0x8]%asi
2209 ldda [%i1+0x20]%asi, %l2
2210 stxa %l5, [%i0+0x10]%asi
2211 stxa %l2, [%i0+0x18]%asi
2213 ldda [%i1+0x30]%asi, %l4
[all …]
H A Dniagara2_asm.s100 * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI.
120 wr %g0, ASI_BLK_INIT_ST_QUAD_LDD_P, %asi
124 stxa %o2, [%o0+0x0]%asi
125 stxa %o2, [%o0+0x40]%asi
126 stxa %o2, [%o0+0x80]%asi
127 stxa %o2, [%o0+0xc0]%asi
129 stxa %o2, [%o0+0x10]%asi
130 stxa %o2, [%o0+0x20]%asi
131 stxa %o2, [%o0+0x30]%asi
133 stxa %o2, [%o0+0x50]%asi
[all …]
H A Dniagara_asm.s90 * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI.
110 wr %g0, ASI_BLK_INIT_ST_QUAD_LDD_P, %asi
114 stxa %o2, [%o0+0x0]%asi
115 stxa %o2, [%o0+0x40]%asi
116 stxa %o2, [%o0+0x80]%asi
117 stxa %o2, [%o0+0xc0]%asi
119 stxa %o2, [%o0+0x10]%asi
120 stxa %o2, [%o0+0x20]%asi
121 stxa %o2, [%o0+0x30]%asi
123 stxa %o2, [%o0+0x50]%asi
[all …]
/titanic_41/usr/src/uts/sparc/v9/ml/
H A Dsyscall_trap.s113 stxa %g1, [%g3 + TRAP_ENT_TICK]%asi
118 stha %g2, [%g3 + TRAP_ENT_TT]%asi
119 stxa %g7, [%g3 + TRAP_ENT_TSTATE]%asi ! save thread in tstate space
120 stna %sp, [%g3 + TRAP_ENT_SP]%asi
121 stna %o0, [%g3 + TRAP_ENT_F1]%asi
122 stna %o1, [%g3 + TRAP_ENT_F2]%asi
123 stna %o2, [%g3 + TRAP_ENT_F3]%asi
124 stna %o3, [%g3 + TRAP_ENT_F4]%asi
125 stna %o4, [%g3 + TRAP_ENT_TPC]%asi
126 stna %o5, [%g3 + TRAP_ENT_TR]%asi
[all …]
/titanic_41/usr/src/lib/libmvec/common/vis/
H A D__vatan2.S128 wr %g0,0x82,%asi ! set %asi for non-faulting loads
199 lda [%i1]%asi,%f10 ! preload next argument
202 lda [%i1+4]%asi,%f11
211 lda [%i3]%asi,%f18
216 lda [%i3+4]%asi,%f19
230 lda [%i1]%asi,%o0
236 lda [%i3]%asi,%l3
270 lda [%i1]%asi,%f20
279 lda [%i1+4]%asi,%f21
284 lda [%i3]%asi,%f28
[all …]
/titanic_41/usr/src/uts/sun4u/cpu/
H A Dus3_cheetah_asm.s167 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
190 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
230 rd %asi, %g7
231 wr %g0, TRAPTR_ASI, %asi
233 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
235 stha %g4, [%g5 + TRAP_ENT_TL]%asi
237 stha %g4, [%g5 + TRAP_ENT_TT]%asi
239 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
241 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
242 stna %sp, [%g5 + TRAP_ENT_SP]%asi
[all …]
H A Dus3_cheetahplus_asm.s239 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
262 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
309 rd %asi, %g7
310 wr %g0, TRAPTR_ASI, %asi
312 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
314 stha %g4, [%g5 + TRAP_ENT_TL]%asi
316 stha %g4, [%g5 + TRAP_ENT_TT]%asi
318 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
320 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
321 stna %sp, [%g5 + TRAP_ENT_SP]%asi
[all …]
/titanic_41/usr/src/cmd/mdb/sparc/v9/kmdb/
H A Dkmdb_v9asmutil.s95 rdasi(uint32_t asi, uintptr_t va)
102 rd %asi, %o3
103 wr %o0, %asi
104 ldxa [%o1]%asi, %o0
106 wr %o3, %asi
114 wrasi(uint32_t asi, uintptr_t va, uint64_t val)
120 rd %asi, %o3
121 wr %o0, %asi
122 stxa %o2, [%o1]%asi
124 wr %o3, %asi
/titanic_41/usr/src/uts/sun4u/io/pci/
H A Dpci_asm.s74 tst %o3 ! Set up %asi with modifier for
77 mov %g1, %asi
82 ldxa [%o1]%asi, %g1
89 lduwa [%o1]%asi, %g1
96 lduha [%o1]%asi, %g1
101 lduba [%o1]%asi, %g1 ! 8-bit!
132 mov ASI_IOL, %asi
133 mov ASI_IO, %asi
141 stxa %g1, [%o1]%asi
148 stuwa %g1, [%o1]%asi
[all …]
/titanic_41/usr/src/uts/sparc/v9/sys/
H A Dprivregs.h38 #include <v9/sys/asi.h>
147 sta %l0, [SBP + (0*4)]%asi; \
148 sta %l1, [SBP + (1*4)]%asi; \
149 sta %l2, [SBP + (2*4)]%asi; \
150 sta %l3, [SBP + (3*4)]%asi; \
151 sta %l4, [SBP + (4*4)]%asi; \
152 sta %l5, [SBP + (5*4)]%asi; \
153 sta %l6, [SBP + (6*4)]%asi; \
154 sta %l7, [SBP + (7*4)]%asi; \
155 sta %i0, [SBP + (8*4)]%asi; \
[all …]
/titanic_41/usr/src/uts/sun4u/io/px/
H A Dpx_asm_4u.s78 tst %o3 ! Set up %asi with modifier for
81 mov %g1, %asi
86 ldxa [%o1]%asi, %g1
93 lduwa [%o1]%asi, %g1
100 lduha [%o1]%asi, %g1
105 lduba [%o1]%asi, %g1 ! 8-bit!
137 mov %g1, %asi
144 stxa %g1, [%o1]%asi
151 stuwa %g1, [%o1]%asi
158 stuha %g1, [%o1]%asi
[all …]
/titanic_41/usr/src/common/crypto/md5/
H A Dmd5_byteswap.h43 #include <v9/sys/asi.h>
133 * achieved by using the %asi register to specify ASI for the lduwa operations.
160 * This actually sets the ASI register, not necessarily to ASI_PL.
163 set_little(uint8_t asi)
166 "wr %%g0, %0, %%asi\n\t"
168 : "r" (asi));
174 uint8_t asi;
177 "rd %%asi, %0\n\t"
178 : "=r" (asi));
180 return (asi);
[all …]

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