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/linux/arch/arm/mach-mmp/
H A DKconfig29 bool "Support MMP2 (ARMv7) platforms from device tree"
42 bool "Support MMP3 (ARMv7) platforms"
77 Select code specific to MMP2. MMP2 is ARMv7 compatible.
/linux/arch/arm/mach-mstar/
H A DKconfig2 bool "MStar/Sigmastar Armv7 SoC Support"
12 based on Armv7 cores like the Cortex A7 and share the same
H A Dmstarv7.c3 * Device Tree support for MStar/Sigmastar Armv7 SoCs
125 DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
/linux/arch/arm/mach-stm32/
H A DKconfig43 endif # ARMv7-M
60 endif # ARMv7-A
/linux/Documentation/arch/arm/
H A Dmarvell.rst133 Sheeva ARMv7 compatible PJ4B
152 Sheeva ARMv7 compatible Dual-core or Quad-core PJ4B-MP
304 Sheeva ARMv7 compatible Quad-core PJ4C
327 ARMv7 compatible
364 - Core: ARMv7 compatible Sheeva PJ4 core
402 - Core: ARMv7 compatible Sheeva PJ4 88sv581x core
406 - Core: Dual-core ARMv7 compatible Sheeva PJ4C core
409 - Core: ARMv7 compatible Sheeva PJ4 core
412 - Core: Dual-core ARMv7 compatible Sheeva PJ4B-MP core
415 - Core: quad-core ARMv7 Cortex-A7
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer_mmio.yaml23 - arm,armv7-timer-mem
52 supported for 32-bit systems which follow the ARMv7 architected reset
101 compatible = "arm,armv7-timer-mem";
/linux/Documentation/devicetree/bindings/arm/mstar/
H A Dmstar,smpctrl.yaml8 title: MStar/SigmaStar Armv7 SoC SMP control registers
14 MStar/SigmaStar's Armv7 SoCs that have more than one processor
H A Dmstar,l3bridge.yaml8 title: MStar/SigmaStar Armv7 SoC l3bridge
14 MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
/linux/arch/arm/mm/
H A Dproc-v7m.S8 * This is the "shell" of the ARMv7-M processor support.
105 * This should be able to cover all ARMv7-M cores.
179 string cpu_v7m_name "ARMv7-M"
248 * Match any ARMv7-M processor core.
H A Dcache-tauros2.c243 * not complying with all of the other ARMv7 requirements), in tauros2_internal_init()
251 * When Tauros2 is used in an ARMv7 system, the L2 in tauros2_internal_init()
254 * ARMv7 spec to contain fine-grained cache control bits). in tauros2_internal_init()
262 mode = "ARMv7"; in tauros2_internal_init()
H A Dtlb-v7.S6 * Modified for ARMv7 by Catalin Marinas
20 .arch armv7-a
H A Dabort-ev7.S15 .arch armv7-a
/linux/drivers/soc/samsung/
H A DKconfig12 bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST
49 bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST
/linux/Documentation/trace/coresight/
H A Dcoresight-cpu-debug.rst49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
56 detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
/linux/arch/arm/kernel/
H A Dentry-v7m.S7 * Low-level vector interface routines for the ARMv7-M architecture
101 * Register switch for ARMv7-M processors.
/linux/arch/arm/mach-at91/
H A DKconfig88 bool "ARMv7 based Microchip LAN966 SoC family"
94 This enables support for ARMv7 based Microchip LAN966 SoC family.
/linux/arch/arm/mach-sunxi/
H A DMakefile2 CFLAGS_mc_smp.o += -march=armv7-a
/linux/arch/arm/mach-rockchip/
H A DMakefile2 CFLAGS_platsmp.o := -march=armv7-a
/linux/arch/arm/mach-hisi/
H A DMakefile6 CFLAGS_platmcpm.o := -march=armv7-a
/linux/arch/arm64/kernel/
H A Dcompat_alignment.c39 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
75 /* ARMv7 Thumb-2 32-bit LDRD/STRD */ in do_alignment_ldrdstrd()
229 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
230 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
/linux/arch/arm/mach-npcm/
H A Dheadsmp.S9 .arch armv7-a
/linux/arch/arm/mach-exynos/
H A Dexynos-smc.S13 .arch armv7-a
H A DMakefile14 CFLAGS_mcpm-exynos.o += -march=armv7-a
/linux/drivers/pinctrl/samsung/
H A DKconfig19 bool "ARMv7-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST
/linux/arch/arm/mach-imx/
H A Dresume-imx6.S12 .arch armv7-a

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