Searched full:arc700 (Results 1 – 25 of 31) sorted by relevance
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | snps,arc700-intc.yaml | 4 $id: http://devicetree.org/schemas/snps,arc700-intc.yaml#
7 title: ARC700 incore Interrupt Controller
14 to ARC700 core.
21 const: snps,arc700-intc
39 compatible = "snps,arc700-intc";
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| /linux/Documentation/devicetree/bindings/arc/ |
| H A D | pct.txt | 3 The ARC700 can be configured with a pipeline performance monitor for counting
14 "snps,arc700-pct"
19 compatible = "snps,arc700-pct";
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| H A D | axs101.txt | 4 SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon
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| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | snps,arc-timer.yaml | 15 - Found on all ARC CPUs (ARC700/ARCHS)
19 TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
28 Use <16> for ARCHS cores, <3> for ARC700 cores.
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| /linux/arch/arc/boot/dts/ |
| H A D | axc001.dtsi | 37 core_intc: arc700-intc@cpu {
38 compatible = "snps,arc700-intc";
78 compatible = "snps,arc700-pct";
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| H A D | nsim_700.dts | 39 compatible = "snps,arc700-intc";
56 compatible = "snps,arc700-pct";
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| H A D | nsimosci.dts | 42 compatible = "snps,arc700-intc";
85 compatible = "snps,arc700-pct";
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| H A D | abilis_tb10x.dtsi | 73 compatible = "snps,arc700-intc";
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| /linux/arch/arc/kernel/ |
| H A D | intc-compact.c | 54 * ARC700 core includes a simple on-chip intc supporting
130 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
153 * over-written (this is deficiency in ARC700 Interrupt mechanism)
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| /linux/arch/arc/include/asm/ |
| H A D | vermagic.h | 6 #define MODULE_ARCH_VERMAGIC "ARC700"
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| H A D | pgtable-bits-arcv2.h | 7 * page table flags for software walked/managed MMUv3 (ARC700) and MMUv4 (HS)
68 * 1. Although ARC700 can do exclusive execute/write protection (meaning R
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| H A D | barrier.h | 33 * ARCompact based cores (ARC700) only have SYNC instruction which is super
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| H A D | mmu-arcv2.h | 5 * MMUv3 (arc700) / MMUv4 (archs) are software page walked and software managed.
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| H A D | cache.h | 20 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
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| H A D | smp.h | 79 * ARC700 doesn't support atomic Read-Modify-Write ops.
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| H A D | pgtable-levels.h | 16 * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
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| /linux/arch/arc/ |
| H A D | Kconfig | 212 Starting with ARC700 4.9, Cache line length is configurable,
273 Introduced with ARC700 4.10: New Features
448 ARC700 divides the 32 bit phy address space into two equal halves
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| H A D | Makefile | 14 tune-mcpu-def-$(CONFIG_ISA_ARCOMPACT) := -mcpu=arc700
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| /linux/arch/arc/plat-tb10x/ |
| H A D | Kconfig | 18 Abilis Systems. TB10x is based on the ARC700 CPU architecture.
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| /linux/drivers/clocksource/ |
| H A D | arc_timer.c | 7 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
289 * - For ARC700, any write to CTRL reg ACKs it, so just rewrite in timer_irq_handler()
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| /linux/arch/arc/mm/ |
| H A D | mmap.c | 3 * ARC700 mmap
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| H A D | tlbex.S | 45 ; ARC700 Exception Handling doesn't auto-switch stack and it only provides
57 ; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
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| /linux/arch/arc/lib/ |
| H A D | strcmp.S | 6 /* This is optimized primarily for the ARC700.
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| H A D | strchr-700.S | 6 /* ARC700 has a relatively long pipeline and branch prediction, so we want
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| /linux/arch/arc/include/uapi/asm/ |
| H A D | swab.h | 10 * -Support single cycle endian-swap insn in ARC700 4.10
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