Home
last modified time | relevance | path

Searched full:arc700 (Results 1 – 25 of 31) sorted by relevance

12

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsnps,arc700-intc.yaml4 $id: http://devicetree.org/schemas/snps,arc700-intc.yaml#
7 title: ARC700 incore Interrupt Controller
14 to ARC700 core.
21 const: snps,arc700-intc
39 compatible = "snps,arc700-intc";
/linux/Documentation/devicetree/bindings/arc/
H A Dpct.txt3 The ARC700 can be configured with a pipeline performance monitor for counting
14 "snps,arc700-pct"
19 compatible = "snps,arc700-pct";
H A Daxs101.txt4 SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon
/linux/Documentation/devicetree/bindings/timer/
H A Dsnps,arc-timer.yaml15 - Found on all ARC CPUs (ARC700/ARCHS)
19 TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
28 Use <16> for ARCHS cores, <3> for ARC700 cores.
/linux/arch/arc/boot/dts/
H A Daxc001.dtsi37 core_intc: arc700-intc@cpu {
38 compatible = "snps,arc700-intc";
78 compatible = "snps,arc700-pct";
H A Dnsim_700.dts39 compatible = "snps,arc700-intc";
56 compatible = "snps,arc700-pct";
H A Dnsimosci.dts42 compatible = "snps,arc700-intc";
85 compatible = "snps,arc700-pct";
H A Dabilis_tb10x.dtsi73 compatible = "snps,arc700-intc";
/linux/arch/arc/kernel/
H A Dintc-compact.c54 * ARC700 core includes a simple on-chip intc supporting
130 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
153 * over-written (this is deficiency in ARC700 Interrupt mechanism)
/linux/arch/arc/include/asm/
H A Dvermagic.h6 #define MODULE_ARCH_VERMAGIC "ARC700"
H A Dpgtable-bits-arcv2.h7 * page table flags for software walked/managed MMUv3 (ARC700) and MMUv4 (HS)
68 * 1. Although ARC700 can do exclusive execute/write protection (meaning R
H A Dbarrier.h33 * ARCompact based cores (ARC700) only have SYNC instruction which is super
H A Dmmu-arcv2.h5 * MMUv3 (arc700) / MMUv4 (archs) are software page walked and software managed.
H A Dcache.h20 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
H A Dsmp.h79 * ARC700 doesn't support atomic Read-Modify-Write ops.
H A Dpgtable-levels.h16 * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
/linux/arch/arc/
H A DKconfig212 Starting with ARC700 4.9, Cache line length is configurable,
273 Introduced with ARC700 4.10: New Features
448 ARC700 divides the 32 bit phy address space into two equal halves
H A DMakefile14 tune-mcpu-def-$(CONFIG_ISA_ARCOMPACT) := -mcpu=arc700
/linux/arch/arc/plat-tb10x/
H A DKconfig18 Abilis Systems. TB10x is based on the ARC700 CPU architecture.
/linux/drivers/clocksource/
H A Darc_timer.c7 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
289 * - For ARC700, any write to CTRL reg ACKs it, so just rewrite in timer_irq_handler()
/linux/arch/arc/mm/
H A Dmmap.c3 * ARC700 mmap
H A Dtlbex.S45 ; ARC700 Exception Handling doesn't auto-switch stack and it only provides
57 ; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
/linux/arch/arc/lib/
H A Dstrcmp.S6 /* This is optimized primarily for the ARC700.
H A Dstrchr-700.S6 /* ARC700 has a relatively long pipeline and branch prediction, so we want
/linux/arch/arc/include/uapi/asm/
H A Dswab.h10 * -Support single cycle endian-swap insn in ARC700 4.10

12