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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dapll.txt1 Binding for Texas Instruments APLL clock.
6 register-mapped APLL with usually two selectable input clocks
10 modes (locked, low power stop etc.) APLL mostly behaves like
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
20 - reg : address and length of the register set for controlling the APLL.
34 compatible = "ti,dra7-apll-clock";
39 compatible = "ti,omap2-apll-clock";
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dimx7ulp-pcc-clock.yaml54 - description: apll pfd2
55 - description: apll pfd1
56 - description: apll pfd0
H A Dnuvoton,ma35d1-clk.yaml36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti-phy.txt48 * "phy-div" - divider for apll
49 * "div-clk" - apll clock
/freebsd/sys/contrib/device-tree/src/arm64/nuvoton/
H A Dma35d1-som-256m.dts43 <&clk APLL>,
H A Dma35d1-iot-512m.dts43 <&clk APLL>,
/freebsd/sys/dev/clk/rockchip/
H A Drk3328_cru.c253 GATE(0, "core_apll_clk", "apll", 0, 0),
643 PLIST(pll_src_cpll_gpll_apll_p) = {"cpll", "gpll", "apll"};
648 PLIST(pll_src_apll_gpll_dpll_npll_p) = {"apll", "gpll", "dpll", "npll"};
666 static struct rk_clk_pll_def apll = { variable
669 .name = "apll",
809 .alt_parent = 0, /* apll */
829 .clk.pll = &apll
H A Drk3288_cru.c99 GATE(0, "apll_core", "apll", 0, 1),
581 PLL(PLL_APLL, "apll", CRU_APLL_CON(0), 0),
H A Drk3568_cru.c167 PLIST(mux_armclk_p) = { "apll", "gpll" };
199 PLIST(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
293 RK_PLL(PLL_APLL, "apll", mux_pll_p, 0, 0),
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dxlnx-versal-clk.h27 #define APLL 18 macro
H A Dxlnx-zynqmp-clk.h14 #define APLL 2 macro
H A Dnuvoton,ma35d1-clk.h22 #define APLL 11 macro
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-clk-ccf.dtsi261 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7xx-clocks.dtsi1274 apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
1285 compatible = "ti,dra7-apll-clock";
1302 apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
1311 apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
1320 apll_pcie_m2_ck: clock-apll-pcie-m2 {
H A Domap24xx-clocks.dtsi130 compatible = "ti,omap2-apll-clock";
140 compatible = "ti,omap2-apll-clock";
/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dcp110-system-controller.txt35 - 0 0 APLL
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3036.dtsi238 * Fix the emac parent clock is DPLL instead of APLL.