Searched full:apll (Results 1 – 17 of 17) sorted by relevance
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/ |
H A D | apll.txt | 1 Binding for Texas Instruments APLL clock. 6 register-mapped APLL with usually two selectable input clocks 10 modes (locked, low power stop etc.) APLL mostly behaves like 17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock" 20 - reg : address and length of the register set for controlling the APLL. 34 compatible = "ti,dra7-apll-clock"; 39 compatible = "ti,omap2-apll-clock";
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | imx7ulp-pcc-clock.yaml | 54 - description: apll pfd2 55 - description: apll pfd1 56 - description: apll pfd0
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H A D | nuvoton,ma35d1-clk.yaml | 36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
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/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | ti-phy.txt | 48 * "phy-div" - divider for apll 49 * "div-clk" - apll clock
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/freebsd/sys/contrib/device-tree/src/arm64/nuvoton/ |
H A D | ma35d1-som-256m.dts | 43 <&clk APLL>,
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H A D | ma35d1-iot-512m.dts | 43 <&clk APLL>,
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/freebsd/sys/dev/clk/rockchip/ |
H A D | rk3328_cru.c | 253 GATE(0, "core_apll_clk", "apll", 0, 0), 643 PLIST(pll_src_cpll_gpll_apll_p) = {"cpll", "gpll", "apll"}; 648 PLIST(pll_src_apll_gpll_dpll_npll_p) = {"apll", "gpll", "dpll", "npll"}; 666 static struct rk_clk_pll_def apll = { variable 669 .name = "apll", 809 .alt_parent = 0, /* apll */ 829 .clk.pll = &apll
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H A D | rk3288_cru.c | 99 GATE(0, "apll_core", "apll", 0, 1), 581 PLL(PLL_APLL, "apll", CRU_APLL_CON(0), 0),
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H A D | rk3568_cru.c | 167 PLIST(mux_armclk_p) = { "apll", "gpll" }; 199 PLIST(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; 293 RK_PLL(PLL_APLL, "apll", mux_pll_p, 0, 0),
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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
H A D | xlnx-versal-clk.h | 27 #define APLL 18 macro
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H A D | xlnx-zynqmp-clk.h | 14 #define APLL 2 macro
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H A D | nuvoton,ma35d1-clk.h | 22 #define APLL 11 macro
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/ |
H A D | zynqmp-clk-ccf.dtsi | 261 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | dra7xx-clocks.dtsi | 1274 apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { 1285 compatible = "ti,dra7-apll-clock"; 1302 apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { 1311 apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { 1320 apll_pcie_m2_ck: clock-apll-pcie-m2 {
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H A D | omap24xx-clocks.dtsi | 130 compatible = "ti,omap2-apll-clock"; 140 compatible = "ti,omap2-apll-clock";
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/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/ |
H A D | cp110-system-controller.txt | 35 - 0 0 APLL
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/freebsd/sys/contrib/device-tree/src/arm/rockchip/ |
H A D | rk3036.dtsi | 238 * Fix the emac parent clock is DPLL instead of APLL.
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