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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra210-amx.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-amx.yaml#
7 title: Tegra210 AMX
10 The Audio Multiplexer (AMX) block can multiplex up to four input streams
25 pattern: "^amx@[0-9a-f]*$"
29 - const: nvidia,tegra210-amx
31 - const: nvidia,tegra186-amx
32 - const: nvidia,tegra210-amx
33 - const: nvidia,tegra194-amx
35 - const: nvidia,tegra234-amx
36 - const: nvidia,tegra194-amx
[all …]
H A Dnvidia,tegra210-ahub.yaml97 '^amx@[0-9a-f]+$':
99 $ref: nvidia,tegra210-amx.yaml#
H A Dnvidia,tegra210-adx.yaml14 RAM in the AMX except that the data flow direction is reversed.
H A Dnvidia,tegra30-ahub.txt34 - amx
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PreAMXConfig.cpp
H A DX86PreTileConfig.cpp9 /// \file Pass to pre-config the shapes of AMX registers
10 /// AMX register needs to be configured before use. The shapes of AMX register
11 /// are encoded in the 1st and 2nd machine operand of AMX pseudo instructions.
15 /// cannot find a dominating point for all AMX instructions.
18 /// ldtilecfg again after the call instruction if callee clobbers any AMX
107 /// Check if the callee will clobber AMX registers.
117 /// Check if MI is AMX pseudo instruction.
122 // We can simply check if it is AMX instruction by its def. in isAMXInstruction()
129 // PTILESTOREDV is the only exception that doesn't def a AMX register. in isAMXInstruction()
147 /// Try to hoist shapes definded below AMX instructions.
[all …]
H A DX86LowerAMXType.cpp10 /// <256 x i32> is bitcasted to x86_amx on X86, and AMX instruction set only
12 /// is not supported by AMX. Since x86_amx is bitcasted from vector <256 x i32>
13 /// and only AMX intrinsics can operate on the type, we need transform
14 /// load/store <256 x i32> instruction to AMX load/store. If the bitcast can
15 /// not be combined with load/store, we transform the bitcast to amx load/store
19 /// -emit-llvm t.c" + "llc t.ll") we should make sure the amx data is volatile,
20 /// because that is necessary for AMX fast register allocation. (In Fast
22 /// there is no additional register for amx to identify the step in spill.)
69 #define DEBUG_TYPE "lower-amx-type"
84 // the intrinsic must be x86 amx intrinsics. in isAMXIntrinsic()
[all …]
H A DX86FastTileConfig.cpp9 /// \file Pass to config the shape of AMX physical registers
10 /// AMX register need to be configured before use. Before FastRegAllocation pass
87 // It should be AMX pseudo instruction that have shape operand. in isTileDef()
115 // AMX instructions that define tile register. in configBasicBlock()
169 // Early exit in the common case of non-AMX code. in runOnMachineFunction()
H A DX86LowerAMXIntrinsics.cpp1 //===-- X86LowerAMXIntrinsics.cpp -X86 Scalarize AMX Intrinsics------------===//
9 /// \file Pass to transform amx intrinsics to scalar operations.
11 /// optnone attributes. With -O0 or optnone attribute, the def of shape to amx
12 /// intrinsics is near the amx intrinsics code. We are not able to find a
13 /// point which post-dominate all the shape and dominate all amx intrinsics.
14 /// To decouple the dependency of the shape, we transform amx intrinsics
16 /// should improve fast register allocation to allocate amx register.
45 #define DEBUG_TYPE "lower-amx-intrinsics"
57 X86ScalarizeAMX("enable-x86-scalar-amx", cl::init(false), cl::Hidden,
58 cl::desc("X86: enable AMX scalarizition."));
[all …]
H A DX86TileConfig.cpp9 /// \file Pass to config the shape of AMX physical registers
10 /// AMX register need to be configured before use. In X86PreTileConfig pass
81 // Early exit in the common case of non-AMX code. in INITIALIZE_PASS_DEPENDENCY()
H A DX86InstrAMX.td1 //===---- X86InstrAMX.td - AMX Instruction Set Extension --*- tablegen -*--===//
9 // This file describes the instructions that make up the Intel AMX instruction
15 // AMX instructions
199 //AMX-FP16
H A DX86.td259 def FeatureAMXTILE : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
260 "Support AMX-TILE instructions">;
261 def FeatureAMXINT8 : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",
262 "Support AMX-INT8 instructions",
264 def FeatureAMXBF16 : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",
265 "Support AMX-BF16 instructions",
267 def FeatureAMXFP16 : SubtargetFeature<"amx-fp16", "HasAMXFP16", "true",
268 "Support AMX amx-fp16 instructions",
270 def FeatureAMXCOMPLEX : SubtargetFeature<"amx-complex", "HasAMXCOMPLEX", "true",
271 "Support AMX-COMPLEX instructions",
H A DX86InstrInfo.td79 // AMX instructions
H A DX86FastPreTileConfig.cpp181 assert(ST->hasSSE2() && "AMX should assume SSE2 enabled"); in InitializeTileConfigStackSpace()
551 // According to AMX ABI, all the tile registers including config register in configBasicBlock()
657 // Early exit in the common case of non-AMX code. in runOnMachineFunction()
H A DX86LowerTileCopy.cpp9 // This file defines the pass which lower AMX tile copy instructions. Since
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTileShapeInfo.h9 /// \file Shape utility for AMX.
10 /// AMX hardware requires to config the shape of tile data register before use.
11 /// The 2D shape includes row and column. In AMX intrinsics interface the shape
13 /// machine operand of AMX pseudo instructions. ShapeT class is to facilitate
15 /// of AMX pseudo instructions.
H A DPasses.h586 /// The pass transforms load/store <256 x i32> to AMX load/store intrinsics
590 /// The pass transforms amx intrinsics to scalar operation if the function has
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DX86TargetParser.def232 X86_FEATURE_COMPAT(AMX_TILE, "amx-tile", 0)
233 X86_FEATURE_COMPAT(AMX_INT8, "amx-int8", 0)
234 X86_FEATURE_COMPAT(AMX_BF16, "amx-bf16", 0)
250 X86_FEATURE_COMPAT(AMX_FP16, "amx-fp16", 0)
253 X86_FEATURE_COMPAT(AMX_COMPLEX, "amx-complex", 0)
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h1 /*===--------------- amxintrin.h - AMX intrinsics -*- C/C++ -*---------------===
20 __attribute__((__always_inline__, __nodebug__, __target__("amx-tile")))
22 __attribute__((__always_inline__, __nodebug__, __target__("amx-int8")))
24 __attribute__((__always_inline__, __nodebug__, __target__("amx-bf16")))
26 __attribute__((__always_inline__, __nodebug__, __target__("amx-fp16")))
231 /// AMX tile register size can be configured, the maximum size is 16x64=1024
233 /// represent 2D tile and the fixed size is maximum amx tile register size.
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DX86.cpp406 } else if (Feature == "+amx-bf16") { in handleTargetFeatures()
408 } else if (Feature == "+amx-fp16") { in handleTargetFeatures()
410 } else if (Feature == "+amx-int8") { in handleTargetFeatures()
412 } else if (Feature == "+amx-tile") { in handleTargetFeatures()
414 } else if (Feature == "+amx-complex") { in handleTargetFeatures()
1054 .Case("amx-bf16", true) in isValidFeatureName()
1055 .Case("amx-complex", true) in isValidFeatureName()
1056 .Case("amx-fp16", true) in isValidFeatureName()
1057 .Case("amx-int8", true) in isValidFeatureName()
1058 .Case("amx-tile", true) in isValidFeatureName()
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra186.dtsi261 tegra_amx1: amx@2903000 {
262 compatible = "nvidia,tegra186-amx",
263 "nvidia,tegra210-amx";
269 tegra_amx2: amx@2903100 {
270 compatible = "nvidia,tegra186-amx",
271 "nvidia,tegra210-amx";
277 tegra_amx3: amx@2903200 {
278 compatible = "nvidia,tegra186-amx",
279 "nvidia,tegra210-amx";
285 tegra_amx4: amx
[all...]
H A Dtegra234.dtsi307 tegra_amx1: amx@2903000 {
308 compatible = "nvidia,tegra234-amx",
309 "nvidia,tegra194-amx";
315 tegra_amx2: amx@2903100 {
316 compatible = "nvidia,tegra234-amx",
317 "nvidia,tegra194-amx";
323 tegra_amx3: amx@2903200 {
324 compatible = "nvidia,tegra234-amx",
325 "nvidia,tegra194-amx";
331 tegra_amx4: amx
[all...]
H A Dtegra194-p2972-0000.dts224 amx@2903000 {
273 amx@2903100 {
322 amx@2903200 {
371 amx@2903300 {
H A Dtegra194-p3509-0000.dtsi169 amx@2903000 {
218 amx@2903100 {
267 amx@2903200 {
316 amx@2903300 {
H A Dtegra234-p3737-0000+p3701-0000.dts

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