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/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-ahub.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
7 title: Tegra210 AHUB
10 The Audio Hub (AHUB) comprises a collection of hardware accelerators
22 pattern: "^ahub@[0-9a-f]*$"
27 - nvidia,tegra210-ahub
28 - nvidia,tegra186-ahub
29 - nvidia,tegra234-ahub
30 - nvidia,tegra264-ahub
32 - const: nvidia,tegra194-ahub
33 - const: nvidia,tegra186-ahub
[all …]
H A Dnvidia,tegra30-ahub.txt1 NVIDIA Tegra30 AHUB (Audio Hub)
4 - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
5 must contain "nvidia,tegra114-ahub". For Tegra124, must contain
6 "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
9 the AHUB's register blocks.
10 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
12 - interrupts : Should contain AHUB interrupt
58 AHUB client modules need to specify the IDs of their CIFs (Client InterFaces).
59 For RX CIFs, the numbers indicate the register number within AHUB routing
61 For TX CIFs, the numbers indicate the bit position within the AHUB routing
[all …]
H A Dnvidia,tegra30-i2s.yaml38 nvidia,ahub-cif-ids:
39 description: list of AHUB CIF IDs
51 - nvidia,ahub-cif-ids
62 nvidia,ahub-cif-ids = <4 4>;
H A Dnvidia,tegra210-admaif.yaml10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
11 that sends/receives data to/from AHUB must interface through an
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
62 in AHUB (Audio Hub). Each port is capable of data transfers in
H A Dnvidia,tegra210-ope.yaml10 The Output Processing Engine (OPE) is one of the AHUB client. It has
56 to corresponding ACIF output port on AHUB (Audio Hub).
63 input port on AHUB.
H A Dnvidia,tegra-audio-graph-card.yaml96 // The ports are defined for AHUB and its child devices.
97 ahub@702d0800 {
98 compatible = "nvidia,tegra210-ahub";
101 clock-names = "ahub";
H A Dnvidia,tegra210-sfc.yaml51 to corresponding ACIF output port on AHUB (Audio Hub).
58 input port on AHUB.
H A Dnvidia,tegra210-mvc.yaml54 to corresponding ACIF output port on AHUB (Audio Hub).
61 input port on AHUB.
H A Dnvidia,tegra210-i2s.yaml47 modules in AHUB. The Tegra I2S driver sets this clock rate as
83 corresponding AHUB (Audio Hub) ACIF port.
H A Dnvidia,tegra210-peq.yaml14 with Audio Hub (AHUB) via Audio Client Interface (ACIF).
H A Dnvidia,tegra210-mbdrc.yaml11 Processing Engine (OPE) which interfaces with Audio Hub (AHUB) via
H A Dnvidia,tegra210-mixer.yaml49 connected to corresponding ports on AHUB (Audio Hub).
H A Dnvidia,tegra210-adx.yaml52 ports on AHUB (Audio Hub).
H A Dnvidia,tegra210-amx.yaml52 ports on AHUB (Audio Hub).
H A Dnvidia,tegra186-asrc.yaml55 connected to corresponding ports on AHUB (Audio Hub). Additional
H A Dnvidia,tegra210-dmic.yaml66 corresponding AHUB (Audio Hub) ACIF port.
H A Dnvidia,tegra186-dspk.yaml66 corresponding AHUB (Audio Hub) ACIF port.
/linux/sound/soc/tegra/
H A DKconfig48 tristate "Tegra30 AHUB module"
50 Say Y or M if you want to add support for the Tegra30 AHUB module.
63 tristate "Tegra210 AHUB module"
65 Config to enable Audio Hub (AHUB) module, which comprises of a
68 AHUB.
69 Say Y or M if you want to add support for Tegra210 AHUB module.
128 Audio Hub (AHUB). Each ADMA channel that sends/receives data to/
129 from AHUB must interface through an ADMAIF channel. ADMA channel
130 sending data to AHUB pairs with an ADMAIF Tx channel, where as
131 ADMA channel receiving data from AHUB pairs with an ADMAIF Rx
H A Dtegra210_ahub.c3 // tegra210_ahub.c - Tegra210 AHUB driver
21 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); in tegra_ahub_get_value_enum() local
29 for (i = 0; i < ahub->soc_data->reg_count; i++) { in tegra_ahub_get_value_enum()
32 reg = e->reg + (ahub->soc_data->xbar_part_size * i); in tegra_ahub_get_value_enum()
34 reg_val &= ahub->soc_data->mask[i]; in tegra_ahub_get_value_enum()
58 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); in tegra_ahub_put_value_enum() local
82 for (i = 0; i < ahub->soc_data->reg_count; i++) { in tegra_ahub_put_value_enum()
83 update[i].reg = e->reg + (ahub->soc_data->xbar_part_size * i); in tegra_ahub_put_value_enum()
85 update[i].mask = ahub->soc_data->mask[i]; in tegra_ahub_put_value_enum()
2154 { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 },
[all …]
H A Dtegra30_ahub.h3 * tegra30_ahub.h - Definitions for Tegra30 AHUB driver
11 /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */
403 * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs,
405 * XBAR: The core cross-bar component of the AHUB.
503 * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif
505 * the AHUB routing registers.
H A Dtegra210_peq.c73 * Since all ahub non-io modules work under same ahub clock it is not in tegra210_peq_read_ram()
74 * necessary to check ahub read busy bit after every read. in tegra210_peq_read_ram()
370 /* Initialize PEQ AHUB RAM with default params */ in tegra210_peq_component_init()
H A Dtegra210_ope.h69 u32 shift; /* Used as offset for AHUB RAM related programing */
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi890 ahub@70300000 {
891 compatible = "nvidia,tegra124-ahub";
945 nvidia,ahub-cif-ids = <4 4>;
956 nvidia,ahub-cif-ids = <5 5>;
967 nvidia,ahub-cif-ids = <6 6>;
978 nvidia,ahub-cif-ids = <7 7>;
989 nvidia,ahub-cif-ids = <8 8>;
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30.dtsi979 ahub@70080000 {
980 compatible = "nvidia,tegra30-ahub";
1014 nvidia,ahub-cif-ids = <4 4>;
1024 nvidia,ahub-cif-ids = <5 5>;
1034 nvidia,ahub-cif-ids = <6 6>;
1044 nvidia,ahub-cif-ids = <7 7>;
1054 nvidia,ahub-cif-ids = <8 8>;
H A Dtegra124.dtsi1005 ahub@70300000 {
1006 compatible = "nvidia,tegra124-ahub";
1060 nvidia,ahub-cif-ids = <4 4>;
1070 nvidia,ahub-cif-ids = <5 5>;
1080 nvidia,ahub-cif-ids = <6 6>;
1090 nvidia,ahub-cif-ids = <7 7>;
1100 nvidia,ahub-cif-ids = <8 8>;

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