Home
last modified time | relevance | path

Searched full:ae (Results 1 – 25 of 222) sorted by relevance

123456789

/linux/drivers/crypto/intel/qat/qat_common/
H A Dqat_hal.c36 #define AE(handle, ae) ((handle)->hal_handle->aes[ae]) macro
70 unsigned char ae, unsigned int ctx_mask) in qat_hal_set_live_ctx() argument
72 AE(handle, ae).live_ctx_mask = ctx_mask; in qat_hal_set_live_ctx()
77 unsigned char ae, unsigned int csr) in qat_hal_rd_ae_csr() argument
83 value = GET_AE_CSR(handle, ae, csr); in qat_hal_rd_ae_csr()
84 if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS)) in qat_hal_rd_ae_csr()
93 unsigned char ae, unsigned int csr, in qat_hal_wr_ae_csr() argument
99 SET_AE_CSR(handle, ae, csr, value); in qat_hal_wr_ae_csr()
100 if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS)) in qat_hal_wr_ae_csr()
109 unsigned char ae, unsigned char ctx, in qat_hal_get_wakeup_event() argument
[all …]
H A Dqat_uclo.c20 unsigned int ae, unsigned int image_num) in qat_uclo_init_ae_data() argument
27 ae_data = &obj_handle->ae_data[ae]; in qat_uclo_init_ae_data()
141 unsigned char ae, unsigned int addr, in qat_uclo_wr_umem_by_words() argument
152 qat_hal_wr_umem(handle, ae, addr++, 1, &outval); in qat_uclo_wr_umem_by_words()
159 unsigned char ae, in qat_uclo_batch_wr_umem() argument
171 ae = umem_init->ae; in qat_uclo_batch_wr_umem()
175 qat_uclo_wr_umem_by_words(handle, ae, addr, value, size); in qat_uclo_batch_wr_umem()
200 unsigned long ae = 0; in qat_uclo_parse_num() local
210 if ((kstrtoul(buf, 10, &ae))) in qat_uclo_parse_num()
213 *num = (unsigned int)ae; in qat_uclo_parse_num()
[all …]
H A Dicp_qat_hal.h129 #define AE_CSR(handle, ae) \ argument
130 ((char __iomem *)(handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12))
131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) argument
132 #define SET_AE_CSR(handle, ae, csr, val) \ argument
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
135 #define AE_XFER(handle, ae) \ argument
136 ((char __iomem *)(handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12))
137 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \ argument
139 #define SET_AE_XFER(handle, ae, reg, val) \ argument
[all …]
H A Dadf_common_drv.h97 int adf_disable_arb_thd(struct adf_accel_dev *accel_dev, u32 ae, u32 thr);
136 void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
141 unsigned char ae, unsigned int ctx_mask);
143 unsigned int ae);
145 unsigned char ae, enum icp_qat_uof_regtype lm_type,
148 unsigned char ae, unsigned char mode);
150 unsigned char ae, unsigned char mode);
152 unsigned char ae, unsigned int ctx_mask, unsigned int upc);
154 unsigned char ae, unsigned int uaddr,
156 void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
[all …]
H A Dadf_fw_counters.c32 u16 ae; member
41 static void adf_fw_counters_parse_ae_values(struct adf_ae_counters *ae_counters, u32 ae, in adf_fw_counters_parse_ae_values() argument
44 ae_counters->ae = ae; in adf_fw_counters_parse_ae_values()
55 unsigned long ae; in adf_fw_counters_load_from_device() local
64 for_each_set_bit(ae, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { in adf_fw_counters_load_from_device()
68 ret = adf_get_ae_fw_counters(accel_dev, ae, &req_count, &resp_count); in adf_fw_counters_load_from_device()
72 adf_fw_counters_parse_ae_values(&fw_counters->ae_counters[i++], ae, in adf_fw_counters_load_from_device()
100 * for each non-admin AE available through the supplied acceleration device.
169 seq_puts(sfile, "AE "); in qat_fw_counters_seq_show()
176 seq_printf(sfile, "%2d:", ae_counters->ae); in qat_fw_counters_seq_show()
[all …]
H A Dadf_cnv_dbgfs.c67 u16 ae; member
130 seq_puts(sfile, "AE "); in qat_cnv_errors_seq_show()
143 seq_printf(sfile, "%d:", ae_errors->ae); in qat_cnv_errors_seq_show()
164 * Allocates and populates table of CNV errors statistics for each non-admin AE
179 unsigned long ae; in cnv_err_stats_alloc() local
204 for_each_set_bit(ae, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { in cnv_err_stats_alloc()
205 ret = adf_get_cnv_stats(accel_dev, ae, &err_cnt, &latest_err); in cnv_err_stats_alloc()
208 "Failed to get CNV stats for ae %ld, [%d].\n", in cnv_err_stats_alloc()
209 ae, ret); in cnv_err_stats_alloc()
216 err_stats->ae_cnv_errors[i].ae = ae; in cnv_err_stats_alloc()
H A Dadf_accel_engine.c145 u32 ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev); in adf_ae_stop() local
150 for (ae = 0, ae_ctr = 0; ae < max_aes; ae++) { in adf_ae_stop()
151 if (hw_data->ae_mask & (1 << ae)) { in adf_ae_stop()
152 qat_hal_stop(loader_data->fw_loader, ae, 0xFF); in adf_ae_stop()
162 static int adf_ae_reset(struct adf_accel_dev *accel_dev, int ae) in adf_ae_reset() argument
H A Dadf_admin.c113 static int adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev, u32 ae, in adf_put_admin_msg_sync() argument
119 int offset = ae * ADF_ADMINMSG_LEN * 2; in adf_put_admin_msg_sync()
121 int mb_offset = ae * ADF_ADMIN_MAILBOX_STRIDE; in adf_put_admin_msg_sync()
142 request->cmd_id, ae); in adf_put_admin_msg_sync()
160 u32 ae; in adf_send_admin() local
162 for_each_set_bit(ae, &ae_mask, ICP_QAT_HW_AE_DELIMITER) in adf_send_admin()
163 if (adf_put_admin_msg_sync(accel_dev, ae, req, resp) || in adf_send_admin()
235 unsigned long ae; in adf_get_dc_capabilities() local
246 for_each_set_bit(ae, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { in adf_get_dc_capabilities()
247 ret = adf_send_admin(accel_dev, &req, &resp, 1ULL << ae); in adf_get_dc_capabilities()
[all …]
H A Dadf_hw_arbiter.c107 int adf_disable_arb_thd(struct adf_accel_dev *accel_dev, u32 ae, u32 thr) in adf_disable_arb_thd() argument
123 /* Disable scheduling for this particular AE and thread */ in adf_disable_arb_thd()
124 ae_thr_map = *(thd_2_arb_cfg + ae); in adf_disable_arb_thd()
127 WRITE_CSR_ARB_WT2SAM(csr, info.arb_offset, info.wt2sam_offset, ae, in adf_disable_arb_thd()
H A Dadf_heartbeat_inject.c23 static void adf_set_hb_counters_fail(struct adf_accel_dev *accel_dev, u32 ae, in adf_set_hb_counters_fail() argument
30 size_t thr_id = ae * hb_ctrs + thr; in adf_set_hb_counters_fail()
54 /* Ensure we have a valid ae */ in adf_heartbeat_inject_error()
H A Dadf_heartbeat.c140 /* loop through all threads in AE */ in check_ae()
171 size_t ae = 0; in adf_hb_get_status() local
190 for_each_set_bit(ae, &ae_mask, max_aes) { in adf_hb_get_status()
191 ae_offset = size_mul(ae, hb_ctrs); in adf_hb_get_status()
258 /* HB clock may be different than AE clock */ in adf_heartbeat_ms_to_ticks()
/linux/drivers/scsi/esas2r/
H A Desas2r_int.c703 static void esas2r_lun_event(struct esas2r_adapter *a, union atto_vda_ae *ae, in esas2r_lun_event() argument
713 esas2r_trace("ae->lu.dwevent: %x", ae->lu.dwevent); in esas2r_lun_event()
714 esas2r_trace("ae->lu.bystate: %x", ae->lu.bystate); in esas2r_lun_event()
720 if (ae->lu.dwevent & VDAAE_LU_LOST) { in esas2r_lun_event()
723 switch (ae->lu.bystate) { in esas2r_lun_event()
739 memcpy(&t->lu_event, &ae->lu, cplen); in esas2r_lun_event()
751 union atto_vda_ae *ae = in esas2r_ae_complete() local
765 "The AE request response length (%p) is too long: %d", in esas2r_ae_complete()
771 last = ae; in esas2r_ae_complete()
774 while (ae < last) { in esas2r_ae_complete()
[all …]
/linux/net/can/
H A Disotp.c213 static int isotp_send_fc(struct sock *sk, int ae, u8 flowstatus) in isotp_send_fc() argument
247 ncf->len = ae + FC_CONTENT_SZ; in isotp_send_fc()
250 ncf->data[ae] = N_PCI_FC | flowstatus; in isotp_send_fc()
251 ncf->data[ae + 1] = so->rxfc.bs; in isotp_send_fc()
252 ncf->data[ae + 2] = so->rxfc.stmin; in isotp_send_fc()
254 if (ae) in isotp_send_fc()
362 static int isotp_rcv_fc(struct isotp_sock *so, struct canfd_frame *cf, int ae) in isotp_rcv_fc() argument
372 if ((cf->len < ae + FC_CONTENT_SZ) || in isotp_rcv_fc()
374 check_pad(so, cf, ae + FC_CONTENT_SZ, so->opt.rxpad_content))) { in isotp_rcv_fc()
388 so->txfc.bs = cf->data[ae + 1]; in isotp_rcv_fc()
[all …]
/linux/security/selinux/
H A Davc.c56 struct avc_entry ae; member
329 list_add(&dest_xpd->xpd_list, &node->ae.xp_node->xpd_head); in avc_add_xperms_decision()
330 node->ae.xp_node->xp.len++; in avc_add_xperms_decision()
369 node->ae.xp_node = dest; in avc_xperms_populate()
426 avc_xperms_free(node->ae.xp_node); in avc_node_free()
440 avc_xperms_free(node->ae.xp_node); in avc_node_kill()
509 node->ae.ssid = ssid; in avc_node_populate()
510 node->ae.tsid = tsid; in avc_node_populate()
511 node->ae.tclass = tclass; in avc_node_populate()
512 memcpy(&node->ae.avd, avd, sizeof(node->ae.avd)); in avc_node_populate()
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-d4xx.rst62 * - __u32 AE mode
66 * - __u32 AE ROI left
67 - Left border of the AE Region of Interest (all ROI values are in pixels
69 * - __u32 AE ROI right
70 - Right border of the AE Region of Interest
71 * - __u32 AE ROI top
72 - Top border of the AE Region of Interest
73 * - __u32 AE ROI bottom
74 - Bottom border of the AE Region of Interest
153 0x00000008 AE mode
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hns-nic.txt7 - ae-handle: accelerator engine handle for hns,
42 - port-idx-in-ae: is the index of port provided by AE.
44 to the CPU. The port-idx-in-ae can be 0 to 5. Here is the diagram:
55 single NIC connected to this switch. In this case, the port-idx-in-ae
73 ae-handle = <&dsaf0>;
74 port-idx-in-ae = <0>;
/linux/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/
H A Dia_css_s3a_types.h35 * ISP block: S3A1 (3A Support for 3A ver.1 (Histogram is not used for AE))
36 * S3A2 (3A Support for 3A ver.2 (Histogram is used for AE))
42 u32 ae_enable; /** ae enabled in binary,
103 /* This struct should be split into 3, for AE, AWB and AF.
118 * ISP block: S3A1(ae_y_* for AE/AF, awb_lg_* for AWB)
160 * ISP block: S3A1 (3A Support for 3A ver.1) (Histogram is not used for AE)
161 * S3A2 (3A Support for 3A ver.2) (Histogram is used for AE)
168 s32 ae_y; /** Sum of Y in a statistics window, for AE.
205 /* Histogram (Statistics for AE).
H A Dia_css_s3a.host.c106 ia_css_ae_encode(&to->ae, from, sizeof(to->ae)); in ia_css_s3a_encode()
141 const struct sh_css_isp_ae_params *ae, in ia_css_ae_dump() argument
144 if (!ae) return; in ia_css_ae_dump()
146 "ae_y_coef_r", ae->y_coef_r); in ia_css_ae_dump()
148 "ae_y_coef_g", ae->y_coef_g); in ia_css_ae_dump()
150 "ae_y_coef_b", ae->y_coef_b); in ia_css_ae_dump()
207 ia_css_ae_dump(&s3a->ae, level); in ia_css_s3a_dump()
/linux/drivers/net/ethernet/hisilicon/hns3/
H A Dhnae3.c194 /* hnae3_register_ae_algo - register a AE algorithm to hnae3 framework
195 * @ae_algo: AE algorithm
250 /* hnae3_unregister_ae_algo - unregisters a AE algorithm
251 * @ae_algo: the AE algorithm to unregister
288 /* hnae3_register_ae_dev - registers a AE device to hnae3 framework
289 * @ae_dev: the AE device
354 /* hnae3_unregister_ae_dev - unregisters a AE device
355 * @ae_dev: the AE device to unregister
/linux/drivers/net/wireless/realtek/rtw89/
H A DKconfig53 tristate "Realtek 8852AE PCI wireless network (Wi-Fi 6) adapter"
59 Select this option will enable support for 8852AE chipset
99 tristate "Realtek 8922AE PCI wireless network (Wi-Fi 7) adapter"
105 Select this option will enable support for 8922AE chipset
/linux/drivers/staging/media/ipu3/
H A Dipu3-css-params.c2445 acc->ae.grid_cfg = acc_user->ae.grid_cfg; in imgu_css_cfg_acc()
2446 acc->ae.ae_ccm = acc_user->ae.ae_ccm; in imgu_css_cfg_acc()
2448 acc->ae.weights[i] = acc_user->ae.weights[i]; in imgu_css_cfg_acc()
2451 acc->ae.grid_cfg = acc_old->ae.grid_cfg; in imgu_css_cfg_acc()
2452 acc->ae.ae_ccm = acc_old->ae.ae_ccm; in imgu_css_cfg_acc()
2454 acc->ae.weights[i] = acc_old->ae.weights[i]; in imgu_css_cfg_acc()
2460 acc->ae.grid_cfg = imgu_css_ae_grid_defaults; in imgu_css_cfg_acc()
2461 acc->ae.ae_ccm = imgu_css_ae_ccm_defaults; in imgu_css_cfg_acc()
2463 acc->ae.weights[i] = weight_def; in imgu_css_cfg_acc()
2466 b_w_log2 = acc->ae.grid_cfg.block_width_log2; in imgu_css_cfg_acc()
[all …]
/linux/arch/powerpc/perf/
H A Dpower7-pmu.c161 s64 ae; in power7_get_alternatives() local
168 ae = event_alternatives[i][j]; in power7_get_alternatives()
169 if (ae && ae != event) in power7_get_alternatives()
170 alt[nalt++] = ae; in power7_get_alternatives()
173 ae = find_alternative_decode(event); in power7_get_alternatives()
174 if (ae > 0) in power7_get_alternatives()
175 alt[nalt++] = ae; in power7_get_alternatives()
/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhnae.c276 * ae_chain - define ae chain head
317 /* hnae_get_handle - get a handle from the AE
319 * @ae_id: the id of the ae to be used
399 * hnae_ae_register - register a AE engine to hnae framework
400 * @hdev: the hnae ae engine device
435 "has not notifier for AE: %s\n", hdev->name); in hnae_ae_register()
442 * hnae_ae_unregister - unregisters a HNAE AE engine
/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-stats.c227 pbuf->params.ae.exp_mean[i] = in rkisp1_stats_get_aec_meas_v10()
242 pbuf->params.ae.exp_mean[4 * i + 0] = in rkisp1_stats_get_aec_meas_v12()
244 pbuf->params.ae.exp_mean[4 * i + 1] = in rkisp1_stats_get_aec_meas_v12()
246 pbuf->params.ae.exp_mean[4 * i + 2] = in rkisp1_stats_get_aec_meas_v12()
248 pbuf->params.ae.exp_mean[4 * i + 3] = in rkisp1_stats_get_aec_meas_v12()
253 pbuf->params.ae.exp_mean[4 * i + 0] = RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value); in rkisp1_stats_get_aec_meas_v12()
320 bls_val = &pbuf->params.ae.bls_val; in rkisp1_stats_get_bls_meas()
/linux/net/mctp/
H A Daf_mctp.c260 DECLARE_SOCKADDR(struct sockaddr_mctp_ext *, ae, in mctp_recvmsg()
262 msg->msg_namelen = sizeof(*ae); in mctp_recvmsg()
263 ae->smctp_ifindex = cb->ifindex; in mctp_recvmsg()
264 ae->smctp_halen = cb->halen; in mctp_recvmsg()
265 memset(ae->__smctp_pad0, 0x0, sizeof(ae->__smctp_pad0)); in mctp_recvmsg()
266 memset(ae->smctp_haddr, 0x0, sizeof(ae->smctp_haddr)); in mctp_recvmsg()
267 memcpy(ae->smctp_haddr, cb->haddr, cb->halen); in mctp_recvmsg()

123456789