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/linux/drivers/iio/adc/
H A Dingenic-adc.c3 * ADC driver for the Ingenic JZ47xx SoCs
6 * based on drivers/mfd/jz4740-adc.c
9 #include <dt-bindings/iio/adc/ingenic,adc.h>
102 int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
116 struct ingenic_adc *adc = iio_priv(iio_dev); in ingenic_adc_set_adcmd() local
118 mutex_lock(&adc->lock); in ingenic_adc_set_adcmd()
121 readl(adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
128 adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
134 adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
142 adc->base + JZ_ADC_REG_ADCMD); in ingenic_adc_set_adcmd()
[all …]
H A Dmcp3911.c110 int (*config)(struct mcp3911 *adc, bool external_vref);
111 int (*get_osr)(struct mcp3911 *adc, u32 *val);
112 int (*set_osr)(struct mcp3911 *adc, u32 val);
113 int (*enable_offset)(struct mcp3911 *adc, bool enable);
114 int (*get_offset)(struct mcp3911 *adc, int channel, int *val);
115 int (*set_offset)(struct mcp3911 *adc, int channel, int val);
116 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val);
117 int (*get_raw)(struct mcp3911 *adc, int channel, int *val);
137 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) in mcp3911_read() argument
141 reg = MCP3911_REG_READ(reg, adc->dev_addr); in mcp3911_read()
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H A Dad7944.c3 * Analog Devices AD7944/85/86 PulSAR ADC family driver.
174 * is only one supported provider, namely the ADI PULSAR ADC HDL project,
185 static int ad7944_3wire_cs_mode_init_msg(struct device *dev, struct ad7944_adc *adc, in ad7944_3wire_cs_mode_init_msg() argument
188 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns in ad7944_3wire_cs_mode_init_msg()
189 : adc->timing_spec->conv_ns; in ad7944_3wire_cs_mode_init_msg()
190 struct spi_transfer *xfers = adc->xfers; in ad7944_3wire_cs_mode_init_msg()
208 xfers[2].rx_buf = &adc->sample.raw; in ad7944_3wire_cs_mode_init_msg()
212 spi_message_init_with_transfers(&adc->msg, xfers, 3); in ad7944_3wire_cs_mode_init_msg()
214 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); in ad7944_3wire_cs_mode_init_msg()
217 static int ad7944_4wire_mode_init_msg(struct device *dev, struct ad7944_adc *adc, in ad7944_4wire_mode_init_msg() argument
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H A Dlpc18xx_adc.c3 * IIO ADC driver for NXP LPC18xx ADC
26 /* LPC18XX ADC registers and bits */
69 static int lpc18xx_adc_read_chan(struct lpc18xx_adc *adc, unsigned int ch) in lpc18xx_adc_read_chan() argument
74 reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW; in lpc18xx_adc_read_chan()
75 writel(reg, adc->base + LPC18XX_ADC_CR); in lpc18xx_adc_read_chan()
77 ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg, in lpc18xx_adc_read_chan()
80 dev_warn(adc->dev, "adc read timed out\n"); in lpc18xx_adc_read_chan()
91 struct lpc18xx_adc *adc = iio_priv(indio_dev); in lpc18xx_adc_read_raw() local
95 mutex_lock(&adc->lock); in lpc18xx_adc_read_raw()
96 *val = lpc18xx_adc_read_chan(adc, chan->channel); in lpc18xx_adc_read_raw()
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H A Dti-adc0832.c3 * ADC0831/ADC0832/ADC0834/ADC0838 8-bit ADC driver
33 * Max size needed: 16x 1 byte ADC data + 8 bytes timestamp
120 static int adc0831_adc_conversion(struct adc0832 *adc) in adc0831_adc_conversion() argument
122 struct spi_device *spi = adc->spi; in adc0831_adc_conversion()
125 ret = spi_read(spi, &adc->rx_buf, 2); in adc0831_adc_conversion()
132 return (adc->rx_buf[0] << 2 & 0xff) | (adc->rx_buf[1] >> 6); in adc0831_adc_conversion()
135 static int adc0832_adc_conversion(struct adc0832 *adc, int channel, in adc0832_adc_conversion() argument
138 struct spi_device *spi = adc->spi; in adc0832_adc_conversion()
140 .tx_buf = adc->tx_buf, in adc0832_adc_conversion()
141 .rx_buf = adc->rx_buf, in adc0832_adc_conversion()
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H A Dmax1241.c3 * MAX1241 low-power, 12-bit serial ADC
41 static int max1241_read(struct max1241 *adc) in max1241_read() argument
57 .rx_buf = &adc->data, in max1241_read()
62 return spi_sync_transfer(adc->spi, xfers, ARRAY_SIZE(xfers)); in max1241_read()
70 struct max1241 *adc = iio_priv(indio_dev); in max1241_read_raw() local
74 mutex_lock(&adc->lock); in max1241_read_raw()
76 if (adc->shutdown) { in max1241_read_raw()
77 gpiod_set_value(adc->shutdown, 0); in max1241_read_raw()
79 ret = max1241_read(adc); in max1241_read_raw()
80 gpiod_set_value(adc->shutdown, 1); in max1241_read_raw()
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H A Dmcp320x.c8 * Driver for following ADC chips from Microchip Technology's:
72 * struct mcp320x - Microchip SPI ADC instance
74 * @msg: SPI message to select a channel and receive a value from the ADC
80 * @chip_info: ADC properties
120 static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel, in mcp320x_adc_conversion() argument
125 if (adc->chip_info->conv_time) { in mcp320x_adc_conversion()
126 ret = spi_sync(adc->spi, &adc->start_conv_msg); in mcp320x_adc_conversion()
130 usleep_range(adc->chip_info->conv_time, in mcp320x_adc_conversion()
131 adc->chip_info->conv_time + 100); in mcp320x_adc_conversion()
134 memset(&adc->rx_buf, 0, sizeof(adc->rx_buf)); in mcp320x_adc_conversion()
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H A Dti-ads8344.c3 * ADS8344 16-bit 8-Channel ADC driver
26 * Lock protecting access to adc->tx_buff and rx_buff,
76 static int ads8344_adc_conversion(struct ads8344 *adc, int channel, in ads8344_adc_conversion() argument
79 struct spi_device *spi = adc->spi; in ads8344_adc_conversion()
82 adc->tx_buf = ADS8344_START; in ads8344_adc_conversion()
84 adc->tx_buf |= ADS8344_SINGLE_END; in ads8344_adc_conversion()
85 adc->tx_buf |= ADS8344_CHANNEL(channel); in ads8344_adc_conversion()
86 adc->tx_buf |= ADS8344_CLOCK_INTERNAL; in ads8344_adc_conversion()
88 ret = spi_write(spi, &adc->tx_buf, 1); in ads8344_adc_conversion()
94 ret = spi_read(spi, adc->rx_buf, sizeof(adc->rx_buf)); in ads8344_adc_conversion()
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H A Dmcp3422.c95 static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig) in mcp3422_update_config() argument
99 ret = i2c_master_send(adc->i2c, &newconfig, 1); in mcp3422_update_config()
101 adc->config = newconfig; in mcp3422_update_config()
108 static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config) in mcp3422_read() argument
111 u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config); in mcp3422_read()
116 ret = i2c_master_recv(adc->i2c, buf, 4); in mcp3422_read()
120 ret = i2c_master_recv(adc->i2c, buf, 3); in mcp3422_read()
130 static int mcp3422_read_channel(struct mcp3422 *adc, in mcp3422_read_channel() argument
137 mutex_lock(&adc->lock); in mcp3422_read_channel()
139 if (req_channel != MCP3422_CHANNEL(adc->config)) { in mcp3422_read_channel()
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H A Dmax1118.c71 struct max1118 *adc = iio_priv(indio_dev); in max1118_read() local
98 .rx_buf = &adc->data, in max1118_read()
105 ret = spi_sync_transfer(adc->spi, xfers + 1, 2); in max1118_read()
107 ret = spi_sync_transfer(adc->spi, xfers, 3); in max1118_read()
112 return adc->data; in max1118_read()
117 struct max1118 *adc = iio_priv(indio_dev); in max1118_get_vref_mV() local
118 const struct spi_device_id *id = spi_get_device_id(adc->spi); in max1118_get_vref_mV()
127 vref_uV = regulator_get_voltage(adc->reg); in max1118_get_vref_mV()
140 struct max1118 *adc = iio_priv(indio_dev); in max1118_read_raw() local
144 mutex_lock(&adc->lock); in max1118_read_raw()
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H A Dmen_z188_adc.c53 struct z188_adc *adc = iio_priv(iio_dev); in z188_iio_read_raw() local
59 tmp = readw(adc->base + chan->channel * 4); in z188_iio_read_raw()
63 "Oversampling error on ADC channel %d\n", in z188_iio_read_raw()
103 struct z188_adc *adc; in men_z188_probe() local
112 adc = iio_priv(indio_dev); in men_z188_probe()
113 indio_dev->name = "z188-adc"; in men_z188_probe()
119 mem = mcb_request_mem(dev, "z188-adc"); in men_z188_probe()
123 adc->base = ioremap(mem->start, resource_size(mem)); in men_z188_probe()
124 if (adc->base == NULL) in men_z188_probe()
127 men_z188_config_channels(adc->base); in men_z188_probe()
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
7 title: STMicroelectronics STM32 ADC
10 STM32 ADC is a successive approximation analog-to-digital converter.
12 in single, continuous, scan or discontinuous mode. Result of the ADC is
19 Each STM32 ADC block can have up to 3 ADC instances.
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
29 - st,stm32mp1-adc-core
30 - st,stm32mp13-adc-core
37 One or more interrupts for ADC block, depending on part used:
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H A Datmel,sama9260-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/atmel,sama9260-adc.yaml#
7 title: AT91 sama9260 and similar Analog to Digital Converter (ADC)
15 - atmel,at91sam9260-adc
16 - atmel,at91sam9rl-adc
17 - atmel,at91sam9g45-adc
18 - atmel,at91sam9x5-adc
19 - atmel,at91sama5d3-adc
36 atmel,adc-channels-used:
40 atmel,adc-startup-time:
43 Startup Time of the ADC in microseconds as defined in the datasheet
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H A Dqcom,pm8018-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/qcom,pm8018-adc.yaml#
13 The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal
14 oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921.
19 - qcom,pm8018-adc
20 - qcom,pm8038-adc
21 - qcom,pm8058-adc
22 - qcom,pm8921-adc
27 ADC base address in the PMIC, typically 0x197.
62 - adc-channel@c
63 - adc-channel@d
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H A Dti,am3359-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/ti,am3359-adc.yaml#
7 title: TI AM3359 ADC
16 - ti,am3359-adc
17 - ti,am4372-adc
20 - ti,am654-adc
21 - const: ti,am3359-adc
26 ti,adc-channels:
27 description: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and
34 description: List of open delays for each channel of ADC in the order of
35 ti,adc-channels. The value corresponds to the number of ADC clock cycles
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H A Dingenic,adc.yaml5 $id: http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml#
8 title: Ingenic JZ47xx ADC controller IIO
14 Industrial I/O subsystem bindings for ADC controller found in
17 ADC clients must use the format described in
19 giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
24 - ingenic,jz4725b-adc
25 - ingenic,jz4740-adc
26 - ingenic,jz4760-adc
27 - ingenic,jz4760b-adc
28 - ingenic,jz4770-adc
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H A Dst,stm32-dfsdm-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
7 title: STMicroelectronics STM32 DFSDM ADC device driver
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
85 - st,stm32-dfsdm-adc
95 st,adc-channels:
97 List of single-ended channels muxed for this ADC.
99 - For st,stm32-dfsdm-adc: up to 8 channels numbered from 0 to 7.
107 st,adc-channel-names:
129 st,adc-channel-types:
141 st,adc-channel-clk-src:
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H A Dadi,axi-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
7 title: Analog Devices AXI ADC IP core
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
17 interface for the actual ADC, while this IP core will interface
18 to the data-lines of the ADC and handle the streaming of data into
20 In some cases, the AXI ADC interface is used to perform specialized
21 operation to a particular ADC, e.g access the physical bus through
22 specific registers to write ADC registers.
37 - adi,axi-adc-10.0.a
55 adi,adc-dev:
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H A Dx-powers,axp209-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/x-powers,axp209-adc.yaml#
7 title: X-Powers AXP ADC
13 ADC is frequently used as a provider to consumers of the ADC channels.
15 ADC channels and their indexes per variant:
64 - const: x-powers,axp209-adc
65 - const: x-powers,axp221-adc
66 - const: x-powers,axp717-adc
67 - const: x-powers,axp813-adc
70 - const: x-powers,axp803-adc
71 - const: x-powers,axp813-adc
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/linux/drivers/hwmon/
H A Dadcxx.c11 * ADC<bb><c>S<sss>, where
18 * http://www.national.com/ds/DC/ADC<bb><c>S<sss>.pdf
52 struct adcxx *adc = spi_get_drvdata(spi); in adcxx_show() local
58 if (mutex_lock_interruptible(&adc->lock)) in adcxx_show()
61 if (adc->channels == 1) { in adcxx_show()
77 value = value * adc->reference >> 12; in adcxx_show()
80 mutex_unlock(&adc->lock); in adcxx_show()
95 struct adcxx *adc = spi_get_drvdata(spi); in adcxx_max_show() local
98 if (mutex_lock_interruptible(&adc->lock)) in adcxx_max_show()
101 reference = adc->reference; in adcxx_max_show()
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/linux/sound/soc/codecs/
H A Drt5665.c952 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
955 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
958 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
961 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
964 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
979 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
985 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
991 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
1333 /* ADC Digital Volume Control */
1334 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
[all …]
H A Drt5677.c1022 /* ADC Digital Volume Control */
1031 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
1046 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
1054 /* ADC Boost Volume Control */
1055 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
1058 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
1061 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
1064 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
1067 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
1533 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-supermicro-x11spi.dts34 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
35 <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
36 <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
37 <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>;
H A Daspeed-bmc-intel-s2600wf.dts33 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
34 <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
35 <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
36 <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>;
/linux/sound/pci/emu10k1/
H A Dp17v.h39 #define I2C_A_ADC_ADD 0x00000034 /*This is the Device address for ADC */
46 #define I2C_D_ADC_REG_MASK 0xfe000000 /*ADC address register */
47 #define I2C_D_ADC_DAT_MASK 0x01ff0000 /*ADC data register */
49 #define ADC_TIMEOUT 0x00000007 /*ADC Timeout Clock Disable */
50 #define ADC_IFC_CTRL 0x0000000b /*ADC Interface Control */
51 #define ADC_MASTER 0x0000000c /*ADC Master Mode Control */
52 #define ADC_POWER 0x0000000d /*ADC PowerDown Control */
53 #define ADC_ATTEN_ADCL 0x0000000e /*ADC Attenuation ADCL */
54 #define ADC_ATTEN_ADCR 0x0000000f /*ADC Attenuation ADCR */
55 #define ADC_ALC_CTRL1 0x00000010 /*ADC ALC Control 1 */
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