| /freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
| H A D | ARM.cpp | 196 // AAPCS guarantees that sp will be 8-byte aligned on any public interface, in setTargetAttributes()
269 case ARMABIKind::AAPCS: in getABIDefaultCC()
320 if (getABIKind() == ARMABIKind::AAPCS || in classifyHomogeneousAggregate()
395 // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're in classifyArgumentType()
403 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at in classifyArgumentType()
409 getABIKind() == ARMABIKind::AAPCS) { in classifyArgumentType()
594 // Otherwise this is an AAPCS variant. in classifyReturnType()
599 // Check for homogeneous aggregates with AAPCS-VFP. in classifyReturnType()
617 // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4) in classifyReturnType()
721 // Homogeneous aggregates for AAPCS-VFP must have base types of float, in isHomogeneousAggregateBaseType()
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| /freebsd/contrib/llvm-project/clang/lib/Basic/Targets/ |
| H A D | ARM.cpp | 70 // FIXME: Enumerated types are variable width in straight AAPCS. in setABIAAPCS()
295 // The backend is hardwired to assume AAPCS for M-class processors, ensure in ARMTargetInfo()
300 setABI("aapcs"); in ARMTargetInfo()
308 setABI("aapcs"); in ARMTargetInfo()
320 setABI("aapcs-linux"); in ARMTargetInfo()
324 setABI("aapcs"); in ARMTargetInfo()
333 setABI("aapcs-linux"); in ARMTargetInfo()
335 setABI("aapcs"); in ARMTargetInfo()
346 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) in ARMTargetInfo()
371 // The defaults (above) are for AAPCS, check if we need to change them. in setABI()
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| H A D | AArch64.cpp | 134 : TargetInfo(Triple), ABI("aapcs") { in AArch64TargetInfo()
185 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type in AArch64TargetInfo()
207 if (Name != "aapcs" && Name != "aapcs-soft" && Name != "darwinpcs" && in setABI()
216 if (hasFeature("fp") && ABI == "aapcs-soft") { in validateTarget()
217 // aapcs-soft is not allowed for targets with an FPU, to avoid there being in validateTarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.cpp | 61 // AAPCS f64 is in aligned register pairs
164 // Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA
176 // AAPCS HFAs must have 1-4 elements, all of the same type in CC_ARM_AAPCS_Custom_Aggregate()
263 // Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core) in CC_ARM_AAPCS_Custom_Aggregate()
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| H A D | ARMCallingConv.td | 126 // ARM AAPCS (EABI) Calling Convention, common parts
156 // ARM AAPCS (EABI) Calling Convention
203 // ARM AAPCS-VFP (EABI) Calling Convention
274 // AAPCS, and also preserves all floating point registers.
304 // When enforcing an AAPCS compliant frame chain, R11 is used as the frame
306 // This AAPCS alternative makes sure the frame index slots match the push
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| H A D | ARMFeatures.td | 551 // If frame pointers are in use, they must follow the AAPCS definition, which
556 def FeatureAAPCSFrameChain : SubtargetFeature<"aapcs-frame-chain",
558 "Create an AAPCS compliant frame chain">;
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| H A D | ARMTargetMachine.cpp | 134 else if (ABIName.starts_with("aapcs")) in computeTargetABI()
188 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit in computeDataLayout()
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| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | ARMTargetParser.cpp | 545 return "aapcs"; in computeDefaultTargetABI()
551 return "aapcs"; in computeDefaultTargetABI()
563 return "aapcs-linux"; in computeDefaultTargetABI()
566 return "aapcs"; in computeDefaultTargetABI()
572 return "aapcs-linux"; in computeDefaultTargetABI()
573 return "aapcs"; in computeDefaultTargetABI()
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| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | ARMAttributeParser.cpp | 259 static const char *strings[] = {"AAPCS", "AAPCS VFP", "Custom", in ABI_VFP_args()
265 static const char *strings[] = {"AAPCS", "iWMMX", "Custom"}; in ABI_WMMX_args()
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| /freebsd/lib/libc/arm/gen/ |
| H A D | arm_initfini.c | 37 * To properly implement setjmp/longjmp for the ARM AAPCS ABI, it has to be
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| /freebsd/contrib/llvm-project/compiler-rt/lib/hwasan/ |
| H A D | hwasan_exceptions.cpp | 53 // required by AAPCS but is a requirement for HWASAN instrumented functions. in __hwasan_personality_wrapper()
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| /freebsd/contrib/llvm-project/compiler-rt/lib/builtins/arm/ |
| H A D | divsi3.S | 27 // Ok, APCS and AAPCS agree on 32 bit args, so it's safe to use the same routine.
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGRecordLayoutBuilder.cpp | 112 /// Helper function to check if we are targeting AAPCS.
114 return Context.getTargetInfo().getABI().starts_with("aapcs"); in isAAPCS()
742 /// The AAPCS that defines that, when possible, bit-fields should
754 /// -fno-aapcs-bitfield-width.
770 // Info.StorageSize. Since AAPCS uses a different container size (width in computeVolatileBitfields()
790 // packed struct. AAPCS does not define access rules for such cases, we let in computeVolatileBitfields()
824 // The AAPCS acknowledges it and imposes no restritions when the in computeVolatileBitfields()
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| H A D | TargetInfo.h | 439 AAPCS = 0, enumerator
460 AAPCS = 1, enumerator
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| H A D | CGRecordLayout.h | 85 /// single "field" within the LLVM struct type, taking into account the AAPCS
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| /freebsd/crypto/openssl/include/openssl/ |
| H A D | rand.h | 95 __NDK_FPABI__ /* __attribute__((pcs("aapcs"))) on ARM */
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCTargetOptions.h | 114 /// aapcs-linux.
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | Specifiers.h | 285 CC_AAPCS, // __attribute__((pcs("aapcs")))
286 CC_AAPCS_VFP, // __attribute__((pcs("aapcs-vfp")))
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| H A D | CodeGenOptions.def | 426 /// Whether to follow the AAPCS enforcing at least one read before storing to a volatile bitfield
432 /// Whether to not follow the AAPCS that enforces volatile bit-field access width to be
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | psci.yaml | 23 in a manner similar to that specified by AAPCS:
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| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFTypePrinter.cpp | 609 OS << " __attribute__((pcs(\"aapcs\")))"; in appendSubroutineNameAfter()
612 OS << " __attribute__((pcs(\"aapcs-vfp\")))"; in appendSubroutineNameAfter()
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| /freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/ |
| H A D | ARM.cpp | 178 // The backend is hardwired to assume AAPCS for M-class processors, ensure in useAAPCSForMachO()
430 // EABI is always AAPCS, and if it was not marked 'hard', it's softfp in getDefaultFloatABI()
805 if (FrameChainOption.starts_with("aapcs")) in getARMTargetFeatures()
806 Features.push_back("+aapcs-frame-chain"); in getARMTargetFeatures()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.td | 42 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter.
677 // Darwin variants of AAPCS.
706 // guarantees more than a normal AAPCS function. x16 and x17 are used on the
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | CallingConv.h | 157 /// normal C (AAPCS) calling convention for normal functions, but floats are
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| /freebsd/crypto/openssl/Configurations/ |
| H A D | 15-android.conf | 205 # (Latter thanks to __attribute__((pcs("aapcs"))) declaration.)
|