Searched full:a6xx (Results 1 – 16 of 16) sorted by relevance
30 <domain name="A6XX" width="32" prefix="variant" varset="chip">45 <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>157 <reg32 offset="0x0808" name="CP_SQE_CNTL" variants="A6XX-A7XX"/>162 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS" variants="A6XX-A7XX">169 <reg32 offset="0x0821" name="CP_HW_FAULT" variants="A6XX-A7XX"/>170 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT" variants="A6XX-A7XX"/>179 …<reg32 offset="0x0824" name="CP_PROTECT_STATUS" type="a6xx_cp_protect_status" variants="A6XX-A7XX"…181 <reg32 offset="0x0825" name="CP_STATUS_1" variants="A6XX-A7XX"/>194 <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE" variants="A6XX-A7XX"/>195 <reg32 offset="0x0840" name="CP_MISC_CNTL" variants="A6XX-A7XX"/>[all …]
24 <value name="WRITE_PRIMITIVE_COUNTS" value="0x09" variants="A6XX-"/>25 <value name="START_PRIMITIVE_CTRS" value="0x0b" variants="A6XX-"/>26 <value name="STOP_PRIMITIVE_CTRS" value="0x0c" variants="A6XX-"/>53 <value name="WT_DONE_TS" value="0x08" variants="A5XX-A6XX"/>67 <value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-A6XX"/>73 <value name="PC_CCU_INVALIDATE_COLOR" value="0x19" variants="A5XX-A6XX"/>79 <value name="PC_CCU_RESOLVE_TS" value="0x1a" variants="A6XX"/>85 <value name="PC_CCU_FLUSH_DEPTH_TS" value="0x1c" variants="A5XX-A6XX"/>91 <value name="PC_CCU_FLUSH_COLOR_TS" value="0x1d" variants="A5XX-A6XX"/>119 <value name="LRZ_FLUSH_INVALIDATE" value="0x26" variants="A5XX-A6XX"/>[all …]
8 <domain name="A6XX" width="32" prefix="variant" varset="chip">98 <reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A6XX">133 <reg32 offset="0x1f8ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A6XX"/>135 <reg32 offset="0x1f8f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A6XX"/>137 <reg32 offset="0x1f8f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A6XX"/>146 <reg32 offset="0x1f8c3" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A6XX-A7XX"/>148 <reg32 offset="0x1f8c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A6XX-A7XX"/>
12 <value name="A6XX" value="6"/>385 but a6xx.
2528 <doc>Guessing that this is the same as a3xx/a6xx.</doc>
11 #include "a6xx.xml.h"694 .a6xx = &(const struct a6xx_info) {725 .a6xx = &(const struct a6xx_info) {744 .a6xx = &(const struct a6xx_info) {775 .a6xx = &(const struct a6xx_info) {801 .a6xx = &(const struct a6xx_info) {825 .a6xx = &(const struct a6xx_info) {850 .a6xx = &(const struct a6xx_info) {875 .a6xx = &(const struct a6xx_info) {901 .a6xx = &(const struct a6xx_info) {[all …]
26 ADRENO_FW_SQE = 0, /* a6xx */28 ADRENO_FW_GMU = 1, /* a6xx */123 const struct a6xx_info *a6xx; member290 * for all a6xx devices, but probably best to limit this in adreno_patchid()669 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
13 #include "a6xx.xml.h"38 * struct a6xx_info - a6xx specific information from device table
635 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) in a6xx_set_hwcg()662 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); in a6xx_set_hwcg()668 if (!adreno_gpu->info->a6xx->hwcg) { in a6xx_set_hwcg()697 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) in a6xx_set_hwcg()710 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; in a6xx_set_cp_protect()884 reglist = adreno_gpu->info->a6xx->ifpc_reglist; in a7xx_patch_pwrup_reglist()898 reglist = adreno_gpu->info->a6xx->pwrup_reglist; in a7xx_patch_pwrup_reglist()921 dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist; in a7xx_patch_pwrup_reglist()1392 if (adreno_gpu->info->a6xx->prim_fifo_threshold) in hw_init()1394 adreno_gpu->info->a6xx->prim_fifo_threshold); in hw_init()[all …]
89 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a8xx_gpu_get_slice_info()197 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); in a8xx_set_hwcg()228 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; in a8xx_set_cp_protect()347 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a8xx_nonctxt_config()
124 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_set_freq()898 const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx; in a6xx_gmu_fw_start()1214 * Warm boot path does not work on newer A6xx GPUs in a6xx_gmu_resume()1515 /* GMU on A6xx votes perfmode on all valid bandwidth */ in a6xx_gmu_rpmh_bw_votes_init()1702 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_rpmh_votes_init()1801 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_pwrlevels_probe()
10 #include "a6xx.xml.h"
796 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_hfi_send_bw_table()
199 generated/a6xx.xml.h \
272 * switch-over happened early enough in mesa a6xx bringup that we273 * can disallow relocs for a6xx and newer.
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power