Searched full:a6xx (Results 1 – 6 of 6) sorted by relevance
28 <domain name="A6XX" width="32" prefix="variant" varset="chip">43 <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>258 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>260 <reg32 offset="0x0A01" name="CP_APERTURE_CNTL_SQE" variants="A6XX"/>261 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/>362 <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>363 <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>364 <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>365 <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/>366 <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/>[all …]
12 <value name="A6XX" value="6"/>384 but a6xx.
2528 <doc>Guessing that this is the same as a3xx/a6xx.</doc>
124 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_set_freq()853 const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx; in a6xx_gmu_fw_start()1142 * Warm boot path does not work on newer A6xx GPUs in a6xx_gmu_resume()1443 /* GMU on A6xx votes perfmode on all valid bandwidth */ in a6xx_gmu_rpmh_bw_votes_init()1584 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_rpmh_votes_init()1671 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_gmu_pwrlevels_probe()
10 #include "a6xx.xml.h"
284 * switch-over happened early enough in mesa a6xx bringup that we285 * can disallow relocs for a6xx and newer.