Searched full:a6xx (Results 1 – 10 of 10) sorted by relevance
24 <value name="WRITE_PRIMITIVE_COUNTS" value="0x09" variants="A6XX-"/>25 <value name="START_PRIMITIVE_CTRS" value="0x0b" variants="A6XX-"/>26 <value name="STOP_PRIMITIVE_CTRS" value="0x0c" variants="A6XX-"/>53 <value name="WT_DONE_TS" value="0x08" variants="A5XX-A6XX"/>67 <value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-A6XX"/>73 <value name="PC_CCU_INVALIDATE_COLOR" value="0x19" variants="A5XX-A6XX"/>79 <value name="PC_CCU_RESOLVE_TS" value="0x1a" variants="A6XX"/>85 <value name="PC_CCU_FLUSH_DEPTH_TS" value="0x1c" variants="A5XX-A6XX"/>91 <value name="PC_CCU_FLUSH_COLOR_TS" value="0x1d" variants="A5XX-A6XX"/>119 <value name="LRZ_FLUSH_INVALIDATE" value="0x26" variants="A5XX-A6XX"/>[all...]
12 <value name="A6XX" value="6"/>406 but a6xx.
2505 <doc>Guessing that this is the same as a3xx/a6xx.</doc>
11 #include "a6xx.xml.h"694 .a6xx = &(const struct a6xx_info) {725 .a6xx = &(const struct a6xx_info) {744 .a6xx = &(const struct a6xx_info) {775 .a6xx = &(const struct a6xx_info) {801 .a6xx = &(const struct a6xx_info) {825 .a6xx = &(const struct a6xx_info) {850 .a6xx = &(const struct a6xx_info) {875 .a6xx = &(const struct a6xx_info) {901 .a6xx [all...]
89 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a8xx_gpu_get_slice_info() 207 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); in a8xx_set_hwcg() 238 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; in a8xx_set_cp_protect() 367 const struct a6xx_info *info = adreno_gpu->info->a6xx;409 reglist = adreno_gpu->info->a6xx->ifpc_reglist; in a8xx_patch_pwrup_reglist() 423 reglist = adreno_gpu->info->a6xx->pwrup_reglist; in a8xx_patch_pwrup_reglist() 448 dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist; in a8xx_patch_pwrup_reglist()
645 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) in a6xx_set_hwcg() 672 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); in a6xx_set_hwcg() 678 if (!adreno_gpu->info->a6xx->hwcg) { in a6xx_set_hwcg() 707 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) in a6xx_set_hwcg() 720 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; in a6xx_set_cp_protect() 817 reglist = adreno_gpu->info->a6xx->ifpc_reglist; in a6xx_set_ubwc_config() 831 reglist = adreno_gpu->info->a6xx->pwrup_reglist; in a6xx_set_ubwc_config() 854 dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist; in a6xx_set_ubwc_config() 1318 if (adreno_gpu->info->a6xx->prim_fifo_threshold) in hw_init() 1320 adreno_gpu->info->a6xx in hw_init() [all...]
10 #include "a6xx.xml.h"
804 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_hfi_send_bw_table()
268 * switch-over happened early enough in mesa a6xx bringup that we269 * can disallow relocs for a6xx and newer.
38 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)