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/freebsd/share/man/man4/
H A Dsnd_hdsp.467 For ADAT ports, 8 channel, 4 channel and 2 channel formats are supported.
68 The effective number of ADAT channels is 8 channels at single speed
69 (32kHz-48kHz) and 4 channels at double speed (64kHz-96kHz).
70 Only the HDSP 9632 can operate at quad speed (128kHz-192kHz), ADAT is
76 .Xr loader 8
89 .It HDSP 9632 Ta " 16 | 16" Ta " 12 | 12" Ta " 8 | 8"
94 .Xr sysctl 8
H A Dsnd_hdspe.466 For ADAT ports, 8 channel, 4 channel and 2 channel formats are supported.
67 The effective number of ADAT channels is 8 channels at single speed
68 (32kHz-48kHz), 4 channels at double speed (64kHz-96kHz), and 2 channels at
69 quad speed (128kHz-192kHz).
74 .Xr loader 8
92 .Xr sysctl 8
H A Dsnd_emu10kx.478 PCM support is limited to 48kHz/16 bit stereo (192kHz/24 bit part
83 to 48kHz/16 bit stereo (192kHz/24 bit part of this chipset is not supported).
138 you will get one more DSP device that is rate-locked to 48kHz/16bit/mono.
139 This is actually 48kHz/16bit/32 channels on SB Live! cards and
140 48kHz/16bit/64channels on Audigy cards, but the current implementation of
161 DSP inputs 0..8:
179 .Xr mixer 8
221 .Xr sysctl 8
226 .Xr loader 8
230 .Xr sysctl 8
/freebsd/contrib/file/magic/Magdir/
H A Danimation39 >8 string XAVC \b, MPEG v4 system, Sony XAVC Codec
46 >8 string 3g2 \b, MPEG v4 system, 3GPP2
56 >8 string 3ge \b, MPEG v4 system, 3GPP
61 >8 string 3gf \b, MPEG v4 system, 3GPP
63 >8 string 3gg \b, MPEG v4 system, 3GPP
67 >8 string 3gh \b, MPEG v4 system, 3GPP
70 >8 string 3gm \b, MPEG v4 system, 3GPP
73 >8 string 3gp \b, MPEG v4 system, 3GPP
82 >8 string 3gr \b, MPEG v4 system, 3GPP
86 >8 string 3gs \b, MPEG v4 system, 3GPP
[all …]
H A Daudio12 >12 belong 1 8-bit ISDN mu-law,
14 >12 belong 2 8-bit linear PCM [REF-PCM],
26 >12 belong 8 Fragmented sample data,
28 >12 belong 11 8-bit fixed point,
36 >12 belong 23 8-bit ISDN mu-law compressed (CCITT G.721 ADPCM voice enc.),
38 >12 belong 24 compressed (8-bit CCITT G.722 ADPCM)
41 >12 belong 27 8-bit A-law (CCITT G.711),
50 >12 lelong 1 8-bit ISDN mu-law,
52 >12 lelong 2 8-bit linear PCM [REF-PCM],
64 >12 belong 8 Fragmented sample data,
[all …]
/freebsd/contrib/file/magic/scripts/
H A Dcreate_filemagic_flac6 ## >>17 belong&0xfffff0 0x2ee000 \b, 192 kHz
15 ## (16384 kHz = 32 kHz * 512 = 32 * 2^9)
17 ## (22579.2 kHz = 44.1kHz * 512 = 44.1 * 2^9)
20 ## (24576 kHz = 48 kHz * 512 = 48 * 2^9)
41 max_fs_n=$(( 8 * min_fs_n ))
53 ## use bc with sed to convert and format Hz to kHz
58 printf -v line ">>17\tbelong&%#-15x\t%#08x\t%s, %s kHz\n" \
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dti,pcm6240.yaml38 ti,adc3120: Stereo-channel, 768-kHz, Burr-Brown™ audio analog-to-
41 ti,adc5120: 2-Channel, 768-kHz, Burr-Brown™ Audio ADC with 120-dB SNR.
43 ti,adc6120: Stereo-channel, 768-kHz, Burr-Brown™ audio analog-to-
46 ti,dix4192: 216-kHz digital audio converter with Quad-Channel In
49 ti,pcm1690: Automotive Catalog 113dB SNR 8-Channel Audio DAC with
52 ti,pcm3120: Automotive, stereo, 106-dB SNR, 768-kHz, low-power
55 ti,pcm3140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
58 ti,pcm5120: Automotive, stereo, 120-dB SNR, 768-kHz, low-power
61 ti,pcm5140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
64 ti,pcm6120: Automotive, stereo, 123-dB SNR, 768-kHz, low-power
[all …]
H A Dst,stm32-sai.yaml152 - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
153 - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
164 - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
165 - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
H A Dgtm601.txt5 "option,gtm601" = 8kHz mono
6 "broadmobi,bm818" = 48KHz stereo
H A Dnuvoton,nau8325.yaml48 FS range is from 8kHz to 96kHz. And also needs to detect the ratio
50 to make sure data is present. There needs to be at least 8 BCLK
H A Dst,sta32x.txt32 This property has to be specified as '/bits/ 8' value.
41 This properties have to be specified as '/bits/ 8' values.
75 If present, PWM speed mode run on odd speed mode (341.3 kHz) on all
76 channels. If not present, normal PWM spped mode (384 kHz) will be used.
90 st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel
93 st,ch1-output-mapping = /bits/ 8 <0>; // set channel 1 output ch 1
94 st,ch2-output-mapping = /bits/ 8 <0>; // set channel 2 output ch 1
95 st,ch3-output-mapping = /bits/ 8 <0>; // set channel 3 output ch 1
H A Dst,sta350.txt28 This property has to be specified as '/bits/ 8' value.
37 This properties have to be specified as '/bits/ 8' values.
79 If present, PWM speed mode run on odd speed mode (341.3 kHz) on all
80 channels. If not present, normal PWM speed mode (384 kHz) will be used.
110 are 1, 2, 4, 8, 16, 32, 64 and 128.
111 This property has to be specified as '/bits/ 8' value.
120 st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel
123 st,ch1-output-mapping = /bits/ 8 <0>; // set channel 1 output ch 1
124 st,ch2-output-mapping = /bits/ 8 <0>; // set channel 2 output ch 1
125 st,ch3-output-mapping = /bits/ 8 <0>; // set channel 3 output ch 1
H A Dfsl,micfil.yaml51 - description: PLL clock source for 8kHz series
52 - description: PLL clock source for 11kHz series
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-ocores.txt25 Defaults to 100 KHz when the property is not specified
37 frequency is fixed at 100 KHz.
53 reg-shift = <0>; /* 8 bit registers */
54 reg-io-width = <1>; /* 8 bit read/write */
69 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
71 reg-shift = <0>; /* 8 bit registers */
72 reg-io-width = <1>; /* 8 bit read/write */
H A Dopencores,i2c-ocores.yaml45 frequency is fixed at 100 KHz.
98 reg-shift = <0>; /* 8 bit registers */
99 reg-io-width = <1>; /* 8 bit read/write */
109 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
111 reg-shift = <0>; /* 8 bit registers */
112 reg-io-width = <1>; /* 8 bit read/write */
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q.dtsi25 /* kHz uV */
33 /* ARM kHz SOC-PU uV */
62 /* kHz uV */
70 /* ARM kHz SOC-PU uV */
97 /* kHz uV */
105 /* ARM kHz SOC-PU uV */
132 /* kHz uV */
140 /* ARM kHz SOC-PU uV */
217 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
325 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
H A Dimx6dl.dtsi24 /* kHz uV */
30 /* ARM kHz SOC-PU uV */
57 /* kHz uV */
63 /* ARM kHz SOC-PU uV */
130 gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
140 gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
148 gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
154 <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
169 <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
178 <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
H A Dimx6q-cm-fx6.dts89 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
185 /* kHz uV */
192 /* ARM kHz SOC-PU uV */
207 /* kHz uV */
214 /* ARM kHz SOC-PU uV */
229 /* kHz uV */
236 /* ARM kHz SOC-PU uV */
251 /* kHz uV */
258 /* ARM kHz SOC-PU uV */
H A Dimx6dl-b1x5pv2.dtsi21 /* kHz uV */
26 /* ARM kHz SOC-PU uV */
34 /* kHz uV */
39 /* ARM kHz SOC-PU uV */
102 gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>;
216 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
390 no-1-8-v;
H A Dimx6ull.dtsi17 /* kHz uV */
25 /* KHz uV */
40 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml65 0: 8
123 Applies an 8-count offset to all long-term averages upon either ATI or
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
286 3: 500 kHz (125 kHz)
294 Tightens the ATI band from 1/8 to 1/16 of the desired target (ULP and
336 maxItems: 8
349 maxItems: 8
375 enum: [0, 1, 8, 9, 12, 14, 15]
380 8: Self inductance
[all …]
H A Diqs269a.yaml16 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
73 Applies an 8-count offset to all long-term averages upon either ATI or
152 description: Tightens the ATI band from 1/8 to 1/16 of the desired target.
181 1: 8 MHz (2 MHz)
183 3: 2 MHz (500 kHz)
225 maxItems: 8
314 maxItems: 8
326 maxItems: 8
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
[all...]
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rt6245-regulator.yaml39 limit 8A, 14A, 12A, 10A. If this property is missing then keep in
63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
/freebsd/sys/dev/sound/pci/
H A Denvy24ht.h62 /* 00: 24.576MHz(96kHz*256) */
63 /* 01: 49.152MHz(192kHz*256) */
75 #define ENVY24HT_CCSM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */
76 #define ENVY24HT_CCSM_I2S_192KHZ 0x08 /* I2S converter 192kHz sampling rate support */
166 #define ENVY24HT_CHAN_REC_ADC4 8
/freebsd/sys/dev/iicbus/controller/twsi/
H A Dmv_twsi.c81 #define TWSI_BAUD_RATE_SLOW 50000 /* 50kHz */
82 #define TWSI_BAUD_RATE_FAST 100000 /* 100kHz */
159 for (n = 0; n < 8; n++) { in mv_twsi_cal_baud_rate()
209 " %" PRIu32 " kHz (M=%d, N=%d) for slow,\n" in mv_twsi_attach()
210 " %" PRIu32 " kHz (M=%d, N=%d) for fast.\n", in mv_twsi_attach()

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