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/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h60 #define RX_CLKSEL_DSS1 (0x10 << 8)
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
49 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
61 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
98 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
[all …]
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
41 # 8 chars 3 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
83 # 8 chars 3 lines
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_yellow_carp.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
103 #define NUM_DCFCLK_DPM_LEVELS 8
104 #define NUM_DISPCLK_DPM_LEVELS 8
105 #define NUM_DPPCLK_DPM_LEVELS 8
106 #define NUM_SOCCLK_DPM_LEVELS 8
107 #define NUM_VCN_DPM_LEVELS 8
108 #define NUM_SOC_VOLTAGE_LEVELS 8
119 //Freq in MHz
[all …]
H A Dsmu15_driver_if_v15_0_0.h41 uint16_t Freq; // in MHz
46 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
47 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
99 #define NUM_DCFCLK_DPM_LEVELS 8
100 #define NUM_DISPCLK_DPM_LEVELS 8
101 #define NUM_DPPCLK_DPM_LEVELS 8
102 #define NUM_SOCCLK_DPM_LEVELS 8
103 #define NUM_VCN_DPM_LEVELS 8
104 #define NUM_SOC_VOLTAGE_LEVELS 8
105 #define NUM_VPE_DPM_LEVELS 8
[all …]
H A Dsmu11_driver_if_vangogh.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
111 #define NUM_SOC_VOLTAGE_LEVELS 8
124 //Freq in MHz
163 #define THROTTLER_STATUS_BIT_TDC_SOC 8
168 uint16_t GfxclkFrequency; //[MHz]
169 uint16_t SocclkFrequency; //[MHz]
170 uint16_t VclkFrequency; //[MHz]
171 uint16_t DclkFrequency; //[MHz]
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h36 #define NUM_SOCCLK_DPM_LEVELS 8
38 #define NUM_DCLK_DPM_LEVELS 8
39 #define NUM_VCLK_DPM_LEVELS 8
40 #define NUM_DCEFCLK_DPM_LEVELS 8
41 #define NUM_PHYCLK_DPM_LEVELS 8
42 #define NUM_DISPCLK_DPM_LEVELS 8
43 #define NUM_PIXCLK_DPM_LEVELS 8
44 #define NUM_DTBCLK_DPM_LEVELS 8
48 #define NUM_FCLK_DPM_LEVELS 8
84 #define FEATURE_DPM_DCEFCLK_BIT 8
[all …]
H A Dsmu13_driver_if_v13_0_4.h30 #define SMU13_0_4_DRIVER_IF_VERSION 8
46 uint16_t Freq; // in MHz
51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
104 #define NUM_DCFCLK_DPM_LEVELS 8
105 #define NUM_DISPCLK_DPM_LEVELS 8
106 #define NUM_DPPCLK_DPM_LEVELS 8
107 #define NUM_SOCCLK_DPM_LEVELS 8
108 #define NUM_VCN_DPM_LEVELS 8
109 #define NUM_SOC_VOLTAGE_LEVELS 8
[all …]
H A Dsmu12_driver_if.h46 uint16_t Freq; // in MHz
51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
105 #define NUM_DCFCLK_DPM_LEVELS 8
106 #define NUM_SOCCLK_DPM_LEVELS 8
109 #define NUM_VCN_DPM_LEVELS 8
112 uint32_t Freq; // In MHz
165 #define THROTTLER_STATUS_BIT_TDC_SOC 8
172 uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz]
174 uint16_t AverageGfxclkFrequency; //[MHz]
[all …]
H A Dsmu13_driver_if_v13_0_0.h33 #define NUM_SOCCLK_DPM_LEVELS 8
35 #define NUM_DCLK_DPM_LEVELS 8
36 #define NUM_VCLK_DPM_LEVELS 8
37 #define NUM_DISPCLK_DPM_LEVELS 8
38 #define NUM_DPPCLK_DPM_LEVELS 8
39 #define NUM_DPREFCLK_DPM_LEVELS 8
40 #define NUM_DCFCLK_DPM_LEVELS 8
41 #define NUM_DTBCLK_DPM_LEVELS 8
44 #define NUM_FCLK_DPM_LEVELS 8
56 #define FEATURE_DPM_DCN_BIT 8
[all …]
H A Dsmu13_driver_if_v13_0_7.h34 #define NUM_SOCCLK_DPM_LEVELS 8
36 #define NUM_DCLK_DPM_LEVELS 8
37 #define NUM_VCLK_DPM_LEVELS 8
38 #define NUM_DISPCLK_DPM_LEVELS 8
39 #define NUM_DPPCLK_DPM_LEVELS 8
40 #define NUM_DPREFCLK_DPM_LEVELS 8
41 #define NUM_DCFCLK_DPM_LEVELS 8
42 #define NUM_DTBCLK_DPM_LEVELS 8
45 #define NUM_FCLK_DPM_LEVELS 8
57 #define FEATURE_DPM_DCN_BIT 8
[all …]
H A Dsmu11_driver_if_navi10.h33 #define PPTABLE_NV10_SMU_VERSION 8
37 #define NUM_SOCCLK_DPM_LEVELS 8
39 #define NUM_DCLK_DPM_LEVELS 8
40 #define NUM_VCLK_DPM_LEVELS 8
41 #define NUM_DCEFCLK_DPM_LEVELS 8
42 #define NUM_PHYCLK_DPM_LEVELS 8
43 #define NUM_DISPCLK_DPM_LEVELS 8
44 #define NUM_PIXCLK_DPM_LEVELS 8
79 #define FEATURE_MEM_VDDCI_SCALING_BIT 8
182 #define THROTTLER_TEMP_LIQUID0_BIT 8
[all …]
H A Dsmu14_driver_if_v14_0.h31 #define NUM_SOCCLK_DPM_LEVELS 8
33 #define NUM_DCLK_DPM_LEVELS 8
34 #define NUM_VCLK_DPM_LEVELS 8
35 #define NUM_DISPCLK_DPM_LEVELS 8
36 #define NUM_DPPCLK_DPM_LEVELS 8
37 #define NUM_DPREFCLK_DPM_LEVELS 8
38 #define NUM_DCFCLK_DPM_LEVELS 8
39 #define NUM_DTBCLK_DPM_LEVELS 8
42 #define NUM_FCLK_DPM_LEVELS 8
54 #define FEATURE_VMEMP_SCALING_BIT 8
[all …]
/linux/net/mac80211/tests/
H A Dtpe.c34 .desc = "identical 20 MHz",
42 .desc = "identical 40 MHz",
50 .desc = "identical 80+80 MHz",
60 .desc = "identical 320 MHz",
68 .desc = "lower 160 MHz of 320 MHz",
72 .n = 8,
76 .desc = "upper 160 MHz of 320 MHz",
80 .n = 8,
81 .expect = 8,
84 .desc = "upper 160 MHz of 320 MHz, go to 40",
[all …]
/linux/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
62 - .. _BANDWIDTH-8-MHZ:
66 - 8 MHz
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.h47 uint16_t Freq; // in MHz
52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
53 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
105 #define NUM_DCFCLK_DPM_LEVELS 8
106 #define NUM_DISPCLK_DPM_LEVELS 8
107 #define NUM_DPPCLK_DPM_LEVELS 8
108 #define NUM_SOCCLK_DPM_LEVELS 8
109 #define NUM_VCN_DPM_LEVELS 8
110 #define NUM_SOC_VOLTAGE_LEVELS 8
128 //Freq in MHz
[all …]
/linux/drivers/clk/mvebu/
H A Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
97 static const int __initconst mv98dx3236_cpu_mpll_ratios[8][2] = {
102 static const int __initconst mv98dx3236_cpu_ddr_ratios[8][2] = {
[all …]
H A Ddove.c25 * SAR0[8:5] : CPU frequency
26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c90 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
266 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
276 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
284 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
289 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
299 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
304 MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
309 MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
351 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
374 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
[all …]
H A Dclk-exynos4.c127 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
427 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
430 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
432 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
438 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
460 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
463 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
466 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
469 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
472 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
[all …]
H A Dclk-exynos5250.c90 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
99 #define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
266 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
271 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
279 8, 1),
283 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
294 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
315 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
324 MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
330 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dphy_shim.h34 #define RADAR_TYPE_STG2 8 /* staggered-2 radar */
80 /* Index for first 20MHz OFDM SISO rate */
82 /* Index for first 20MHz OFDM CDD rate */
84 /* Index for first 40MHz OFDM SISO rate */
86 /* Index for first 40MHz OFDM CDD rate */
88 #define WL_TX_POWER_OFDM_NUM 8
89 /* Index for first 20MHz MCS SISO rate */
91 /* Index for first 20MHz MCS CDD rate */
93 /* Index for first 20MHz MCS STBC rate */
95 /* Index for first 20MHz MCS SDM rate */
[all …]
/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c17 * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
26 * ref_freq = 28.636360 MHz
28 * ref_freq = 28.636363 MHz
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
47 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
53 * 196.6 MHz pre-postdivide in cx25840_set_audclk_freq()
54 * FIXME < 200 MHz is out of specified valid range in cx25840_set_audclk_freq()
69 /* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */ in cx25840_set_audclk_freq()
84 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
85 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
[all …]
/linux/Documentation/admin-guide/media/
H A Ddvb_intro.rst107 Seven 177.500 Mhz
108 SBS 184.500 Mhz
109 Nine 191.625 Mhz
110 Ten 219.500 Mhz
111 ABC 226.500 Mhz
112 Channel 31 557.625 Mhz
133 T 177500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
134 T 184500000 7MHz AUTO AUTO QAM64 8k 1/8 NONE
135 T 191625000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
136 T 219500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
[all …]
/linux/drivers/net/wireless/ti/wl12xx/
H A Dwl12xx.h48 #define WL12XX_NUM_RX_DESCRIPTORS 8
54 #define WL12XX_MAX_AP_STATIONS 8
73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
[all …]

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