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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
44 * Bank type for non-alive type. Bit fields:
64 /* pin banks of exynos5433 pin-controller - ALIVE */
67 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
68 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
69 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
70 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
[all …]
H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
77 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
79 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
83 return ERR_PTR(-ENODEV); in s5pv210_retention_init()
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3_lcd.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,sama5d3-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
H A Dat91sam9x5_lcd.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,at91sam9x5-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rza1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
11 * This includes SoCs which are sub- or super- sets of this particular line,
22 #include <linux/pinctrl/pinconf-generic.h>
34 #define DRIVER_NAME "pinctrl-rza1"
56 * Use 16 lower bits [15:0] for pin identifier
57 * Use 16 higher bits [31:16] for pin mux function
69 /* Pin mux flags */
74 /* ----------------------------------------------------------------------------
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H A Dpinctrl-rza2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
25 #define DRIVER_NAME "pinctrl-rza2"
27 #define RZA2_PINS_PER_PORT 8
32 * Use 16 lower bits [15:0] for pin identifier
33 * Use 16 higher bits [31:16] for pin mux function
54 #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
55 #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
56 #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
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/linux/drivers/gpio/
H A Dgpio-zynqmp-modepin.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the ps-mode pin configuration.
16 #include <linux/firmware/xlnx-zynqmp.h>
18 /* 4-bit boot mode pins */
22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device
24 * @pin: gpio pin number within the device
26 * This function reads the state of the specified pin of the GPIO device.
28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured
31 static int modepin_gpio_get_value(struct gpio_chip *chip, unsigned int pin) in modepin_gpio_get_value() argument
40 /* When [0:3] corresponding bit is set, then read output bit [8:11], in modepin_gpio_get_value()
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/linux/Documentation/driver-api/
H A Dpin-control.rst2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,mxs-pinctrl.txt1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
20 information about pull-up. For this reason, even seemingly boolean values are
[all …]
H A Dsunplus,sp7021-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 Pin Controller
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
23 (1) function-group pins:
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250-artik5.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
26 stdout-path = &serial_2;
35 compatible = "samsung,secure-firmware";
39 thermal-zones {
40 cpu_thermal: cpu-thermal {
41 cooling-maps {
44 cooling-device = <&cpu0 5 5>,
[all …]
H A Ds3c64xx-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
16 * Pin banks
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
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H A Ds5pv210-aries.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
32 reserved-memory {
33 #address-cells = <1>;
34 #size-cells = <1>;
38 compatible = "shared-dma-pool";
39 no-map;
44 compatible = "shared-dma-pool";
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H A Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/input/input.h>
19 chassis-type = "laptop";
33 stdout-path = "serial3:115200n8";
36 gpio-keys {
37 compatible = "gpio-keys";
[all …]
H A Dexynos4210-i9100.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
21 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
38 vemmc_reg: regulator-0 {
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/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal2_scratch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 reg << 8); in mv88e6xxx_g2_scratch_read()
38 u16 value = (reg << 8) | data; in mv88e6xxx_g2_scratch_write()
45 * mv88e6xxx_g2_scratch_get_bit - get a bit
55 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_get_bit()
70 * mv88e6xxx_g2_scratch_set_bit - set (or clear) a bit
82 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_set_bit()
100 * mv88e6352_g2_scratch_gpio_get_data - get data on gpio pin
102 * @pin: gpio index
107 unsigned int pin) in mv88e6352_g2_scratch_gpio_get_data() argument
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/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
32 /* LPC18XX SCU pin register definitions */
40 #define LPC18XX_SCU_PIN_EHD_POS 8
50 #define LPC18XX_SCU_I2C0_SDA_SHIFT 8
52 #define LPC18XX_SCU_FUNC_PER_PIN 8
54 /* LPC18XX SCU pin interrupt select registers */
61 #define LPC18XX_GPIO_PIN_INT_MAX 8
64 ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
66 /* LPC18xx pin types */
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H A Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
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H A Dpinctrl-aw9523.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Awinic AW9523B i2c pin controller driver
22 #include <linux/pinctrl/pinconf-generic.h>
29 #define AW9523_PINS_PER_PORT 8
32 * HW needs at least 20uS for reset and at least 1-2uS to recover from
40 /* Port 0: P0_0...P0_7 - Port 1: P1_0...P1_7 */
41 #define AW9523_PIN_TO_PORT(pin) (pin >> 3) argument
42 #define AW9523_REG_IN_STATE(pin) (0x00 + AW9523_PIN_TO_PORT(pin)) argument
43 #define AW9523_REG_OUT_STATE(pin) (0x02 + AW9523_PIN_TO_PORT(pin)) argument
44 #define AW9523_REG_CONF_STATE(pin) (0x04 + AW9523_PIN_TO_PORT(pin)) argument
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/linux/arch/arm64/boot/dts/actions/
H A Ds900-bubblegum-96.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "ucrobotics,bubblegum-96", "actions,s900";
12 model = "Bubblegum-96";
22 stdout-path = "serial5:115200n8";
31 vcc_3v1: vcc-3v1 {
32 compatible = "regulator-fixed";
33 regulator-name = "fixed-3.1V";
34 regulator-min-microvolt = <3100000>;
35 regulator-max-microvolt = <3100000>;
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Dpincfg.txt1 * Pin configuration nodes
4 - pio-map : array of pin configurations. Each pin is defined by 6
5 integers. The six numbers are respectively: port, pin, dir,
7 - port : port number of the pin; 0-6 represent port A-G in UM.
8 - pin : pin number in the port.
9 - dir : direction of the pin, should encode as follows:
11 0 = The pin is disabled
12 1 = The pin is an output
13 2 = The pin is an input
14 3 = The pin is I/O
[all …]
/linux/sound/pci/lola/
H A Dlola_mixer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for Digigram Lola PCI-e boards
18 static int lola_init_pin(struct lola *chip, struct lola_pin *pin, in lola_init_pin() argument
24 pin->nid = nid; in lola_init_pin()
27 dev_err(chip->card->dev, "Can't read wcaps for 0x%x\n", nid); in lola_init_pin()
32 pin->is_analog = false; in lola_init_pin()
34 pin->is_analog = true; in lola_init_pin()
36 pin->is_analog = true; in lola_init_pin()
38 dev_err(chip->card->dev, "Invalid wcaps 0x%x for 0x%x\n", val, nid); in lola_init_pin()
39 return -EINVAL; in lola_init_pin()
[all …]
/linux/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-core.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2015-2017 Socionext Inc.
13 #include <linux/pinctrl/pinconf-generic.h>
19 #include "../pinctrl-utils.h"
20 #include "pinctrl-uniphier.h"
49 return priv->socdata->groups_count; in uniphier_pctl_get_groups_count()
57 return priv->socdata->groups[selector].name; in uniphier_pctl_get_group_name()
67 *pins = priv->socdata->groups[selector].pins; in uniphier_pctl_get_group_pins()
68 *num_pins = priv->socdata->groups[selector].num_pins; in uniphier_pctl_get_group_pins()
80 switch (uniphier_pin_get_pull_dir(desc->drv_data)) { in uniphier_pctl_pin_dbg_show()
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/linux/Documentation/devicetree/bindings/net/
H A Dmdio-mux-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
31 - gpios
36 - |
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/linux/drivers/pinctrl/bcm/
H A Dpinctrl-ns2-mux.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * corresponding mfio pin group is selected as gpio.
16 #include <linux/pinctrl/pinconf-generic.h>
22 #include "../pinctrl-utils.h"
87 * Northstar2 mux function and supported pin groups
133 * Pin configuration info
139 * @pull_shift: pull-up/pull-down control bit shift in the register
152 * Description of a pin in Northstar2
154 * @pin: pin number
155 * @name: pin name
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