| /linux/Documentation/networking/ |
| H A D | 6pack.rst | 4 6pack Protocol
7 This is the 6pack-mini-HOWTO, written by
17 1. What is 6pack, and what are the advantages to KISS?
20 6pack is a transmission protocol for data exchange between the PC and
21 the TNC over a serial line. It can be used as an alternative to KISS.
23 6pack has two major advantages:
27 that the PC knows at any time if the TNC is receiving data, if a TNC
29 set and so on. This control data is processed at a higher priority than
30 normal data, so a data stream can be interrupted at any time to issue an
36 TNCs that are connected between each other and the PC by a daisy chain
[all …]
|
| /linux/tools/testing/selftests/net/ |
| H A D | fcnal-test.sh | 13 # 6. VRF and non-VRF permutations
16 # ns-A | ns-B
23 # ns-A:
35 # ns-A to ns-C connection - only for VRF and same config
36 # as ns-A to ns-B
38 # server / client nomenclature relative to ns-A
215 if [ "$VERBOSE" = "1" -a -n "$out" ]; then
253 read a
275 read a
297 read a
[all...] |
| /linux/drivers/net/ethernet/marvell/octeontx2/af/cn20k/ |
| H A D | reg.h | 15 #define RVU_PRIV_PFX_DISC(a) (0x8000208 | (a) << 16) argument
16 #define RVU_PRIV_HWVFX_DISC(a) (0xD000000 | (a) << 12) argument
20 #define RVU_MBOX_AF_PFX_ADDR(a) (0x5000 | (a) << 4) argument
21 #define RVU_MBOX_AF_PFX_CFG(a) (0x6000 | (a) << 4) argument
22 #define RVU_MBOX_AF_AFPFX_TRIGX(a) (0x9000 | (a) << 3) argument
23 #define RVU_MBOX_AF_PFAF_INT(a) (0x2980 | (a) << 6) argument
24 #define RVU_MBOX_AF_PFAF_INT_W1S(a) (0x2988 | (a) << 6) argument
25 #define RVU_MBOX_AF_PFAF_INT_ENA_W1S(a) (0x2990 | (a) << 6) argument
26 #define RVU_MBOX_AF_PFAF_INT_ENA_W1C(a) (0x2998 | (a) << 6) argument
27 #define RVU_MBOX_AF_PFAF1_INT(a) (0x29A0 | (a) << 6) argument
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ |
| H A D | mapfile.csv | 2 GenuineIntel-6-(97|9A|B7|BA|BF),v1.34,alderlake,core
3 GenuineIntel-6-BE,v1.34,alderlaken,core
4 GenuineIntel-6-C[56],v1.13,arrowlake,core
5 GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
6 GenuineIntel-6-(3D|47),v30,broadwell,core
7 GenuineIntel-6-56,v12,broadwellde,core
8 GenuineIntel-6-4F,v23,broadwellx,core
9 GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core
10 GenuineIntel-6-DD,v1.00,clearwaterforest,core
11 GenuineIntel-6-9[6C],v1.05,elkhartlake,core
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
24 "Counter": "0,1,2,3,4,5,6,7",
27 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
34 "Counter": "0,1,2,3,4,5,6,7,8,9",
37 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
44 "Counter": "0,1,2,3,4,5,6,7,8,9",
53 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
|
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
46 "Counter": "0,1,2,3,4,5,6,7,8,9",
49 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
56 "Counter": "0,1,2,3,4,5,6,7,8,9",
65 "Counter": "0,1,2,3,4,5,6,7",
68 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
41 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
52 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
42 "Counter": "0,1,2,3,4,5,6,7",
50 "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
[all …]
|
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7,8,9",
64 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
81 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
82 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
|
| H A D | other.json | 3 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
4 "Counter": "0,1,2,3,4,5,6,7,8,9",
7 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
22 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progr…
23 "Counter": "0,1,2,3,4,5,6,7",
26 …Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another…
32 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted loc…
33 "Counter": "0,1,2,3,4,5,6,7",
36 …r of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
42 "Counter": "0,1,2,3,4,5,6,7",
50 "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
[all …]
|
| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
12 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
13 "Counter": "0,1,2,3,4,5,6,7",
22 "Counter": "0,1,2,3,4,5,6,7,8,9",
31 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
32 "Counter": "0,1,2,3,4,5,6,7,8,9",
36 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
43 "Counter": "0,1,2,3,4,5,6,7",
52 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 … evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) li…
13 "Counter": "0,1,2,3,4,5,6,7",
16 … of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
22 "Counter": "0,1,2,3,4,5,6,7",
25 …er of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
31 "Counter": "0,1,2,3,4,5,6,7",
34 …r of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
40 "Counter": "0,1,2,3,4,5,6,7",
43 …ber of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
[all …]
|
| /linux/Documentation/userspace-api/media/rc/ |
| H A D | rc-protos.rst | 9 IR is encoded as a series of pulses and spaces, using a protocol. These
10 protocols can encode e.g. an address (which device should respond) and a
12 across different devices for a given protocol.
14 Therefore out the output of the IR decoder is a scancode; a single u32
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
22 Some remotes have a pointer-type device which can used to control the
32 This IR protocol uses manchester encoding to encode 14 bits. There is a
55 - 6 (inverted)
57 - 2nd start bit in rc5, re-used as 6th command bit
71 * - 6
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 … evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) li…
13 "Counter": "0,1,2,3,4,5,6,7",
16 … of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
22 "Counter": "0,1,2,3,4,5,6,7",
25 …er of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
31 "Counter": "0,1,2,3,4,5,6,7",
34 …r of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
40 "Counter": "0,1,2,3,4,5,6,7",
43 …ber of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
27 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
46 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
84 …of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots…
85 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3,4,5,6,7",
34 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
35 "Counter": "0,1,2,3,4,5,6,7",
38 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
45 "Counter": "0,1,2,3,4,5,6,7",
49 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
55 "Counter": "0,1,2,3,4,5,6,7",
64 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/testing/selftests/drivers/net/mlxsw/ |
| H A D | devlink_trap_control.sh | 98 ip -6 route add default vrf v$h1 nexthop via 2001:db8:1::2
103 ip -6 route del default vrf v$h1 nexthop via 2001:db8:1::2
114 ip -6 route add default vrf v$h2 nexthop via 2001:db8:2::2
119 ip -6 route del default vrf v$h2 nexthop via 2001:db8:2::2
222 $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
223 -A 192.0.2.1 -B 224.0.0.1 -t ip proto=2,p=11 -p 100 -q
230 "igmp_v1_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
231 -A 192.0.2.1 -B 244.0.0.1 -t ip proto=2,p=12 -p 100 -q
238 "igmp_v2_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
239 -A 192.0.2.1 -B 244.0.0.1 -t ip proto=2,p=16 -p 100 -q
[all …]
|
| /linux/lib/crypto/x86/ |
| H A D | sha256-avx-asm.S | 11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
47 # This code schedules 1 block at a time, with 4 lanes per block
106 a = %eax define
140 # Rotate values of symbols a...h
149 b = a
150 a = TMP_ define
154 ## compute s0 four at a time and s1 two at a time
155 ## compute W[-16] + W[-7] 4 at a time
159 mov a, y1 # y1 = a
[all …]
|
| H A D | sha256-ssse3-asm.S | 11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
99 a = %eax define
134 # Rotate values of symbols a...h
143 b = a
144 a = TMP_ define
148 ## compute s0 four at a time and s1 two at a time
149 ## compute W[-16] + W[-7] 4 at a time
153 mov a, y1 # y1 = a
155 ror $(22-13), y1 # y1 = a >> (22-13)
[all …]
|
| /linux/tools/thermal/tmon/ |
| H A D | tmon.8 | 4 \fBtmon\fP - A monitoring and testing tool for Linux kernel thermal subsystem
32 - with a built-in Proportional Integral Derivative (\fBPID\fP)
33 controller, user can pair a cooling device to a thermal sensor for
46 The \fB-c --control\fP option sets a cooling device type to control temperature
47 of a thermal zone
70 \fBA \fP active cooling trip point type (fan)
72 \fBA \fP hot trip point type
89 \fBTAB\fP shows tuning pop up panel, choose a letter to modify
115 LCD14 intel_powerclamp15 1 65.0 65 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 2
116 65.0 66 65 0 0 0 0 0 0 0 0 0 0 4 4 4 4 6 0 3 65.0 60 54 0 0 0 0 0 0 0 0
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|