| /linux/Documentation/networking/ |
| H A D | 6pack.rst | 4 6pack Protocol
7 This is the 6pack-mini-HOWTO, written by
17 1. What is 6pack, and what are the advantages to KISS?
20 6pack is a transmission protocol for data exchange between the PC and
21 the TNC over a serial line. It can be used as an alternative to KISS.
23 6pack has two major advantages:
27 that the PC knows at any time if the TNC is receiving data, if a TNC
29 set and so on. This control data is processed at a higher priority than
30 normal data, so a data stream can be interrupted at any time to issue an
36 TNCs that are connected between each other and the PC by a daisy chain
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| /linux/tools/testing/selftests/net/ |
| H A D | fcnal-test.sh | 13 # 6. VRF and non-VRF permutations
16 # ns-A | ns-B
23 # ns-A:
35 # ns-A to ns-C connection - only for VRF and same config
36 # as ns-A to ns-B
38 # server / client nomenclature relative to ns-A
215 if [ "$VERBOSE" = "1" -a -n "$out" ]; then
253 read a
275 read a
297 read a
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| /linux/tools/perf/pmu-events/arch/x86/ |
| H A D | mapfile.csv | 2 GenuineIntel-6-(97|9A|B7|BA|BF),v1.27,alderlake,core
3 GenuineIntel-6-BE,v1.27,alderlaken,core
4 GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
5 GenuineIntel-6-(3D|47),v29,broadwell,core
6 GenuineIntel-6-56,v11,broadwellde,core
7 GenuineIntel-6-4F,v22,broadwellx,core
8 GenuineIntel-6-55-[56789ABCDEF],v1.22,cascadelakex,core
9 GenuineIntel-6-9[6C],v1.05,elkhartlake,core
10 GenuineIntel-6-CF,v1.09,emeraldrapids,core
11 GenuineIntel-6-5[CF],v13,goldmont,core
[all …]
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| /linux/Documentation/dev-tools/ |
| H A D | kmemleak.rst | 4 Kmemleak provides a way of detecting possible kernel memory leaks in a
5 way similar to a `tracing garbage collector
8 reported via /sys/kernel/debug/kmemleak. A similar method is used by the
15 CONFIG_DEBUG_KMEMLEAK in "Kernel hacking" has to be enabled. A kernel
58 trigger a memory scan
86 information like size and stack trace, are stored in a rbtree.
94 block to a freeing function and therefore the block is considered a
103 a pointer to a white object is found, the object is added to the
115 block is not considered a leak. One example is __vmalloc().
124 /sys/kernel/debug/kmemleak output. By issuing a 'scan' after a 'clear'
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| /linux/Documentation/userspace-api/media/rc/ |
| H A D | rc-protos.rst | 9 IR is encoded as a series of pulses and spaces, using a protocol. These
10 protocols can encode e.g. an address (which device should respond) and a
12 across different devices for a given protocol.
14 Therefore out the output of the IR decoder is a scancode; a single u32
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
22 Some remotes have a pointer-type device which can used to control the
32 This IR protocol uses manchester encoding to encode 14 bits. There is a
55 - 6 (inverted)
57 - 2nd start bit in rc5, re-used as 6th command bit
71 * - 6
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| /linux/Documentation/input/devices/ |
| H A D | elantech.rst | 24 5.2 Native absolute mode 6 byte packet format
28 6. Hardware version 3
30 6.2 Native absolute mode 6 byte packet format
35 7.2 Native absolute mode 6 byte packet format
41 8.2 Native relative mode 6 byte packet format
52 packet. Version 2 seems to be introduced with the EeePC and uses 6 bytes
54 and width of the touch. Hardware version 3 uses 6 bytes per packet (and
55 for 2 fingers the concatenation of two 6 bytes packets) and allows tracking
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
57 combine a status packet with multiple head or motion packets. Hardware version
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| /linux/tools/testing/selftests/drivers/net/mlxsw/ |
| H A D | devlink_trap_control.sh | 98 ip -6 route add default vrf v$h1 nexthop via 2001:db8:1::2
103 ip -6 route del default vrf v$h1 nexthop via 2001:db8:1::2
114 ip -6 route add default vrf v$h2 nexthop via 2001:db8:2::2
119 ip -6 route del default vrf v$h2 nexthop via 2001:db8:2::2
222 $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
223 -A 192.0.2.1 -B 224.0.0.1 -t ip proto=2,p=11 -p 100 -q
230 "igmp_v1_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
231 -A 192.0.2.1 -B 244.0.0.1 -t ip proto=2,p=12 -p 100 -q
238 "igmp_v2_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
239 -A 192.0.2.1 -B 244.0.0.1 -t ip proto=2,p=16 -p 100 -q
[all …]
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| /linux/arch/x86/crypto/ |
| H A D | sha256-avx-asm.S | 11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
47 # This code schedules 1 block at a time, with 4 lanes per block
107 a = %eax define
141 # Rotate values of symbols a...h
150 b = a
151 a = TMP_ define
155 ## compute s0 four at a time and s1 two at a time
156 ## compute W[-16] + W[-7] 4 at a time
160 mov a, y1 # y1 = a
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|
| H A D | sha256-ssse3-asm.S | 11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
100 a = %eax define
135 # Rotate values of symbols a...h
144 b = a
145 a = TMP_ define
149 ## compute s0 four at a time and s1 two at a time
150 ## compute W[-16] + W[-7] 4 at a time
154 mov a, y1 # y1 = a
156 ror $(22-13), y1 # y1 = a >> (22-13)
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| H A D | frontend.json | 7 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
39 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
62 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
63 "Counter": "0,1,2,3,4,5,6,7",
69 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
75 "Counter": "0,1,2,3,4,5,6,7",
87 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3,4,5,6,7",
34 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
35 "Counter": "0,1,2,3,4,5,6,7",
38 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
45 "Counter": "0,1,2,3,4,5,6,7",
48 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
54 "Counter": "0,1,2,3,4,5,6,7",
64 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
27 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
46 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
53 "Counter": "0,1,2,3,4,5,6,7",
66 "Counter": "0,1,2,3,4,5,6,7",
78 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
79 "Counter": "0,1,2,3,4,5,6,7",
85 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
[all …]
|
| /linux/tools/thermal/tmon/ |
| H A D | tmon.8 | 4 \fBtmon\fP - A monitoring and testing tool for Linux kernel thermal subsystem
32 - with a built-in Proportional Integral Derivative (\fBPID\fP)
33 controller, user can pair a cooling device to a thermal sensor for
46 The \fB-c --control\fP option sets a cooling device type to control temperature
47 of a thermal zone
70 \fBA \fP active cooling trip point type (fan)
72 \fBA \fP hot trip point type
89 \fBTAB\fP shows tuning pop up panel, choose a letter to modify
115 LCD14 intel_powerclamp15 1 65.0 65 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 2
116 65.0 66 65 0 0 0 0 0 0 0 0 0 0 4 4 4 4 6 0 3 65.0 60 54 0 0 0 0 0 0 0 0
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| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| H A D | frontend.json | 7 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
39 "Counter": "0,1,2,3,4,5,6,7",
50 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
51 "Counter": "0,1,2,3,4,5,6,7",
57 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
63 "Counter": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
87 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| H A D | frontend.json | 7 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
39 "Counter": "0,1,2,3,4,5,6,7",
50 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
51 "Counter": "0,1,2,3,4,5,6,7",
57 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
63 "Counter": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
87 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/arch/powerpc/crypto/ |
| H A D | aes-tab-4k.S | 10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
35 .long R(ff, f2, f2, 0d), R(d6, 6b, 6b, bd)
36 .long R(de, 6f, 6f, b1), R(91, c5, c5, 54)
40 .long R(4d, ab, ab, e6), R(ec, 76, 76, 9a)
50 .long R(3d, 93, 93, ae), R(4c, 26, 26, 6a)
51 .long R(6c, 36, 36, 5a), R(7e, 3f, 3f, 41)
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
16 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
16 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|