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/linux/lib/raid6/
H A Drecov_avx512.c62 asm volatile("vpbroadcastb %0, %%zmm7" : : "m" (x0f)); in raid6_2data_recov_avx512()
75 : "m" (q[0]), "m" (q[64]), "m" (p[0]), in raid6_2data_recov_avx512()
76 "m" (p[64]), "m" (dq[0]), "m" (dq[64]), in raid6_2data_recov_avx512()
77 "m" (dp[0]), "m" (dp[64])); in raid6_2data_recov_avx512()
81 * 9 = dq[64] ^ q[64] in raid6_2data_recov_avx512()
83 * 8 = dp[64] ^ p[64] in raid6_2data_recov_avx512()
89 : "m" (qmul[0]), "m" (qmul[16])); in raid6_2data_recov_avx512()
108 * 15 = qx[64] in raid6_2data_recov_avx512()
126 : "m" (pbmul[0]), "m" (pbmul[16])); in raid6_2data_recov_avx512()
130 * 13 = pbmul[px[64]] in raid6_2data_recov_avx512()
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H A Davx512.c57 : "m" (raid6_avx512_constants.x1d[0])); in raid6_avx5121_gen_syndrome()
59 for (d = 0; d < bytes; d += 64) { in raid6_avx5121_gen_syndrome()
66 : "m" (dptr[z0][d]), "m" (dptr[z0-1][d])); in raid6_avx5121_gen_syndrome()
78 : "m" (dptr[z][d])); in raid6_avx5121_gen_syndrome()
92 : "m" (p[d]), "m" (q[d])); in raid6_avx5121_gen_syndrome()
113 : : "m" (raid6_avx512_constants.x1d[0])); in raid6_avx5121_xor_syndrome()
115 for (d = 0 ; d < bytes ; d += 64) { in raid6_avx5121_xor_syndrome()
120 : "m" (dptr[z0][d]), "m" (p[d])); in raid6_avx5121_xor_syndrome()
133 : "m" (dptr[z][d])); in raid6_avx5121_xor_syndrome()
151 : "m" (q[d]), "m" (p[d])); in raid6_avx5121_xor_syndrome()
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H A Drecov_loongarch_simd.c69 asm volatile("vld $vr20, %0" : : "m" (qmul[0])); in raid6_2data_recov_lsx()
70 asm volatile("vld $vr21, %0" : : "m" (qmul[16])); in raid6_2data_recov_lsx()
71 asm volatile("vld $vr22, %0" : : "m" (pbmul[0])); in raid6_2data_recov_lsx()
72 asm volatile("vld $vr23, %0" : : "m" (pbmul[16])); in raid6_2data_recov_lsx()
76 asm volatile("vld $vr4, %0" : : "m" (q[0])); in raid6_2data_recov_lsx()
77 asm volatile("vld $vr5, %0" : : "m" (q[16])); in raid6_2data_recov_lsx()
78 asm volatile("vld $vr6, %0" : : "m" (q[32])); in raid6_2data_recov_lsx()
79 asm volatile("vld $vr7, %0" : : "m" (q[48])); in raid6_2data_recov_lsx()
81 asm volatile("vld $vr8, %0" : : "m" (dq[0])); in raid6_2data_recov_lsx()
82 asm volatile("vld $vr9, %0" : : "m" (dq[16])); in raid6_2data_recov_lsx()
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H A Drecov_avx2.c53 asm volatile("vpbroadcastb %0, %%ymm7" : : "m" (x0f)); in raid6_2data_recov_avx2()
57 asm volatile("vmovdqa %0, %%ymm1" : : "m" (q[0])); in raid6_2data_recov_avx2()
58 asm volatile("vmovdqa %0, %%ymm9" : : "m" (q[32])); in raid6_2data_recov_avx2()
59 asm volatile("vmovdqa %0, %%ymm0" : : "m" (p[0])); in raid6_2data_recov_avx2()
60 asm volatile("vmovdqa %0, %%ymm8" : : "m" (p[32])); in raid6_2data_recov_avx2()
61 asm volatile("vpxor %0, %%ymm1, %%ymm1" : : "m" (dq[0])); in raid6_2data_recov_avx2()
62 asm volatile("vpxor %0, %%ymm9, %%ymm9" : : "m" (dq[32])); in raid6_2data_recov_avx2()
63 asm volatile("vpxor %0, %%ymm0, %%ymm0" : : "m" (dp[0])); in raid6_2data_recov_avx2()
64 asm volatile("vpxor %0, %%ymm8, %%ymm8" : : "m" (dp[32])); in raid6_2data_recov_avx2()
73 asm volatile("vbroadcasti128 %0, %%ymm4" : : "m" (qmul[0])); in raid6_2data_recov_avx2()
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H A Davx2.c46 asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0])); in raid6_avx21_gen_syndrome()
50 asm volatile("prefetchnta %0" : : "m" (dptr[z0][d])); in raid6_avx21_gen_syndrome()
51 asm volatile("vmovdqa %0,%%ymm2" : : "m" (dptr[z0][d]));/* P[0] */ in raid6_avx21_gen_syndrome()
52 asm volatile("prefetchnta %0" : : "m" (dptr[z0-1][d])); in raid6_avx21_gen_syndrome()
54 asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z0-1][d])); in raid6_avx21_gen_syndrome()
56 asm volatile("prefetchnta %0" : : "m" (dptr[z][d])); in raid6_avx21_gen_syndrome()
63 asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z][d])); in raid6_avx21_gen_syndrome()
72 asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d])); in raid6_avx21_gen_syndrome()
74 asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d])); in raid6_avx21_gen_syndrome()
95 asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0])); in raid6_avx21_xor_syndrome()
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/linux/arch/m68k/fpsp040/
H A Dstwotox.S15 | 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the
29 | 3. Decompose X as X = N/64 + r where |r| <= 1/128. Furthermore
31 | N = 64(M + M') + j, j = 0,1,2,...,63.
34 | 2**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r).
42 | 3. Set y := X*log_2(10)*64 (base 2 log of 10). Set
44 | N = 64(M + M') + j, j = 0,1,2,...,63.
48 | where L1, L2 are the leading and trailing parts of log_10(2)/64
50 | 10**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r).
54 | 1. Fetch 2**(j/64) from table as Fact1 and Fact2.
57 | Fact1 := 2**(M) * Fact1
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H A Dsetox.S20 | The returned result is within 0.85 ulps in 64 significant bit, i.e.
79 | Step 2. Calculate N = round-to-nearest-int( X * 64/log2 ).
81 | 2.2 N := round-to-nearest-integer( X * 64/log2 ).
82 | 2.3 Calculate J = N mod 64; so J = 0,1,2,..., or 63.
83 | 2.4 Calculate M = (N - J)/64; so N = 64M + J.
84 | 2.5 Calculate the address of the stored value of 2^(J/64).
85 | 2.6 Create the value Scale = 2^M.
93 | constant := single-precision( 64/log 2 ).
99 | Z = X*(64/log2)*(1+eps), |eps| <= 2^(-24).
103 | Step 3. Calculate X - N*log2/64.
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/linux/Documentation/scsi/
H A Daic7xxx.rst35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
36 aic7892 20 PCI/64-66 80MHz 16Bit 16 3 4 5 6 7 8
40 aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8
41 aic7899 20 PCI/64-66 80MHz 16Bit 16 2 3 4 5 6 7 8
49 4. 64 Byte SCB Support - Allows disconnected, untagged request table
63 AHA-274X[A] aic7770 EISA SE-50M SE-HD50F
65 SE-50M
66 AHA-274X[A]T aic7770 EISA 2 X SE-50M SE-HD50F
67 AHA-2842 aic7770 VL SE-50M SE-HD50F
68 AHA-2940AU aic7860 PCI/32 SE-50M SE-HD50F
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044-cpus.dtsi18 i-cache-block-size = <64>;
21 d-cache-block-size = <64>;
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
40 riscv,cbom-block-size = <64>;
41 riscv,cbop-block-size = <64>;
42 riscv,cboz-block-size = <64>;
54 i-cache-block-size = <64>;
57 d-cache-block-size = <64>;
65 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
76 riscv,cbom-block-size = <64>;
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/linux/lib/
H A Dsiphash.c15 #if defined(CONFIG_DCACHE_WORD_ACCESS) && BITS_PER_LONG == 64
50 u64 m; in __siphash_aligned() local
53 m = le64_to_cpup(data); in __siphash_aligned()
54 v3 ^= m; in __siphash_aligned()
57 v0 ^= m; in __siphash_aligned()
59 #if defined(CONFIG_DCACHE_WORD_ACCESS) && BITS_PER_LONG == 64 in __siphash_aligned()
83 u64 m; in __siphash_unaligned() local
86 m = get_unaligned_le64(data); in __siphash_unaligned()
87 v3 ^= m; in __siphash_unaligned()
90 v0 ^= m; in __siphash_unaligned()
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/linux/lib/math/
H A Dint_sqrt.c22 unsigned long b, m, y = 0; in int_sqrt() local
27 m = 1UL << (__fls(x) & ~1UL); in int_sqrt()
28 while (m != 0) { in int_sqrt()
29 b = y + m; in int_sqrt()
34 y += m; in int_sqrt()
36 m >>= 2; in int_sqrt()
43 #if BITS_PER_LONG < 64
45 * int_sqrt64 - strongly typed int_sqrt function when minimum 64 bit input
47 * @x: 64bit integer of which to calculate the sqrt
51 u64 b, m, y = 0; in int_sqrt64() local
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/linux/arch/mips/loongson2ef/common/
H A Dpci.c37 * CPU address space [256M,448M] is window for accessing pci space in setup_pcimap()
38 * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] in setup_pcimap()
41 * [<2G] [384M,448M] [320M,384M] [0M,64M] in setup_pcimap()
49 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] in setup_pcimap()
51 LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ in setup_pcimap()
52 /* size: 256M, burst transmission, pre-fetch enable, 64bit */ in setup_pcimap()
/linux/arch/parisc/kernel/
H A Dpacache.S86 pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */
100 pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */
130 pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */
144 pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */
207 fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */
216 fice,m %arg1(%sr1, %arg0)
217 fice,m %arg1(%sr1, %arg0)
218 fice,m %arg1(%sr1, %arg0)
219 fice,m %arg1(%sr1, %arg0)
220 fice,m %arg1(%sr1, %arg0)
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/linux/drivers/mfd/
H A Dmcp-sa11x0.c35 #define MCCR0(m) ((m)->base0 + 0x00) argument
36 #define MCDR0(m) ((m)->base0 + 0x08) argument
37 #define MCDR1(m) ((m)->base0 + 0x0c) argument
38 #define MCDR2(m) ((m)->base0 + 0x10) argument
39 #define MCSR(m) ((m)->base0 + 0x18) argument
40 #define MCCR1(m) ((m)->base1 + 0x00) argument
47 struct mcp_sa11x0 *m = priv(mcp); in mcp_sa11x0_set_telecom_divisor() local
51 m->mccr0 &= ~0x00007f00; in mcp_sa11x0_set_telecom_divisor()
52 m->mccr0 |= divisor << 8; in mcp_sa11x0_set_telecom_divisor()
53 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_set_telecom_divisor()
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Dmsm_media_info.h184 * M M M M M M M M M M M M . . ^ ^
185 * M M M M M M M M M M M M . . | |
186 * M M M M M M M M M M M M . . Height |
187 * M M M M M M M M M M M M . . | Meta_Y_Scanlines
188 * M M M M M M M M M M M M . . | |
189 * M M M M M M M M M M M M . . | |
190 * M M M M M M M M M M M M . . | |
191 * M M M M M M M M M M M M . . V |
211 * M M M M M M M M M M M M . . ^
212 * M M M M M M M M M M M M . . |
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/linux/arch/mips/math-emu/
H A Dieee754sp.h36 /* 64 bit right shift with rounding */
38 (((rs) >= 64) ? ((v) != 0) : ((v) >> (rs)) | ((v) << (64-(rs)) != 0))
44 #define XSPSRS1(m) \ argument
45 ((m >> 1) | (m & 1))
54 #define SPDNORMx(m,e) \ argument
55 while ((m >> SP_FBITS) == 0) { m <<= 1; e--; }
60 static inline union ieee754sp buildsp(int s, int bx, unsigned int m) in buildsp() argument
67 assert(((m) >> SP_FBITS) == 0); in buildsp()
71 r.mant = m; in buildsp()
/linux/arch/x86/include/asm/
H A Dsyscall_wrapper.h17 * __x64_sys_*() - 64-bit native syscall
20 * __x64_compat_sys_*() - 64-bit X32 compat syscall
23 * 64-bit: RDI, RSI, RDX, R10, R8, R9
48 * cltq <-- extend return value to 64-bit
55 /* Mapping of registers to parameters for syscalls on x86-64 and x32 */
63 #define SYSCALL_PT_ARG6(m, t1, t2, t3, t4, t5, t6) \ argument
64 SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5), m(t6, (regs->bp))
65 #define SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5) \ argument
66 SYSCALL_PT_ARG4(m, t1, t2, t3, t4), m(t5, (regs->di))
67 #define SYSCALL_PT_ARG4(m, t1, t2, t3, t4) \ argument
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/linux/arch/mips/include/asm/
H A Dcmpxchg.h34 #define __xchg_asm(ld, st, m, val) \ argument
36 __typeof(*(m)) __ret; \
52 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
53 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \
59 __ret = *m; \
60 *m = val; \
112 #define __cmpxchg_asm(ld, st, m, old, new) \ argument
114 __typeof(*(m)) __ret; \
132 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
133 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
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/linux/Documentation/arch/powerpc/
H A Dkaslr-booke32.rst24 We will use the first 512M of the low memory to randomize the kernel
25 image. The memory will be split in 64M zones. We will use the lower 8
26 bit of the entropy to decide the index of the 64M zone. Then we chose a
27 16K aligned offset inside the 64M zone to put the kernel in::
31 |--> 64M <--|
/linux/tools/testing/selftests/nolibc/
H A DMakefile.nolibc36 # ppc64 | powerpc | 64 bits big endian
37 # ppc64le | powerpc | 64 bits little endian
109 DEFCONFIG_mipsn32le = malta_defconfig generic/64r2.config
110 DEFCONFIG_mipsn32be = malta_defconfig generic/64r6.config generic/eb.config
111 DEFCONFIG_mips64le = malta_defconfig generic/64r6.config
112 DEFCONFIG_mips64be = malta_defconfig generic/64r2.config generic/eb.config
180 QEMU_ARGS_i386 = -M pc -append "console=ttyS0,9600 i8042.noaux panic=-1 $(TEST:%=NOLIBC_TEST=%)"
181 QEMU_ARGS_x86_64 = -M pc -append "console=ttyS0,9600 i8042.noaux panic=-1 $(TEST:%=NOLIBC_TEST=%)"
182 QEMU_ARGS_x32 = -M pc -append "console=ttyS0,9600 i8042.noaux panic=-1 $(TEST:%=NOLIBC_TEST=%)"
183 QEMU_ARGS_x86 = -M p
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/linux/arch/powerpc/include/asm/
H A Dpage.h19 * On regular PPC32 page size is 4K (but we support 4K/16K/64K/256K pages
20 * on PPC44x and 4K/16K on 8xx). For PPC64 we support either 4K or 64K software
21 * page size. When using 64K pages however, whether we are really supporting
22 * 64K pages in HW or not is irrelevant to those definitions.
35 #define HPAGE_SHIFT 22 /* 4M pages */
128 * virtual_base = ALIGN_DOWN(KERNELBASE,256M) +
129 * MODULO(_stext.run,256M)
132 * ALIGN_DOWN(_stext.run,256M) => ALIGN_DOWN(KERNELBASE,256M)
150 * Let the kernel be loaded at 64MB and KERNELBASE be 0xc0000000 (same as PAGE_OFFSET).
151 * In this case, we would be mapping 0 to 0xc0000000, and kernstart_addr = 64M
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/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,imx-weim.yaml69 05 128M 0M 0M 0M
70 033 64M 64M 0M 0M
71 0113 64M 32M 32M 0M
72 01111 32M 32M 32M 32M
/linux/drivers/media/platform/verisilicon/
H A Dhantro_vp9.c28 height32 = roundup(h, 64); in hantro_vp9_tile_filter_size()
39 height32 = roundup(h, 64); in hantro_vp9_bsd_control_size()
51 num_ctbs = ((w + 63) / 64) * ((h + 63) / 64); in hantro_vp9_segment_map_size()
71 static void *get_coeffs_arr(struct symbol_counts *cnts, int i, int j, int k, int l, int m) in get_coeffs_arr() argument
74 return &cnts->count_coeffs[j][k][l][m]; in get_coeffs_arr()
77 return &cnts->count_coeffs8x8[j][k][l][m]; in get_coeffs_arr()
80 return &cnts->count_coeffs16x16[j][k][l][m]; in get_coeffs_arr()
83 return &cnts->count_coeffs32x32[j][k][l][m]; in get_coeffs_arr()
88 static void *get_eobs1(struct symbol_counts *cnts, int i, int j, int k, int l, int m) in get_eobs1() argument
91 return &cnts->count_coeffs[j][k][l][m][3]; in get_eobs1()
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/linux/include/linux/
H A Djiffies.h75 * The 64-bit value is not atomic on 32-bit systems - you MUST NOT read it
80 * and for 64-bit big-endian systems.
88 #if (BITS_PER_LONG < 64)
92 * get_jiffies_64 - read the 64-bit non-atomic jiffies_64 value
94 * When BITS_PER_LONG < 64, this uses sequence number sampling using
95 * jiffies_lock to protect the 64-bit read.
97 * Return: current 64-bit jiffies value
184 /* Same as above, but does so with platform independent 64bit types.
375 * do this and pass the 64-bit result of the mpy through the ">> SCALE"
382 * For those who want to know, gcc will give a 64-bit result from a "*"
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/linux/crypto/
H A Daegis128-neon-inner.c38 vld1q_u8(state + 64) in aegis128_load_state_neon()
48 vst1q_u8(state + 64, st.v[4]); in aegis128_save_state_neon()
108 uint8x16_t m) in aegis128_update_neon() argument
110 m ^= aegis_aes_round(st.v[4]); in aegis128_update_neon()
115 st.v[0] ^= m; in aegis128_update_neon()
128 asm("ld1 {v16.16b-v19.16b}, [%0], #64 \n\t" in preload_sbox()
129 "ld1 {v20.16b-v23.16b}, [%0], #64 \n\t" in preload_sbox()
130 "ld1 {v24.16b-v27.16b}, [%0], #64 \n\t" in preload_sbox()
179 * implement the underlying instructions. AArch32 only provides 64-bit
216 static const uint8_t permute[] __aligned(64) = {
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