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/freebsd/sys/x86/iommu/
H A Dintel_quirks.c187 .descr = "5500 E47, E53" /* interrupt remapping does not work */
192 .descr = "5500 E47, E53" /* interrupt remapping does not work */
197 .descr = "5500 E47, E53" /* interrupt remapping does not work */
202 .descr = "5500 E47, E53" /* interrupt remapping does not work */
/freebsd/sys/dev/ath/ath_hal/ah_regdomain/
H A Dah_rd_freqbands.h128 { 5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC },
131 { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI },
134 { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
136 { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },
138 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },
140 { 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC },
189 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Delpida_ecb240abacn.dtsi37 tDQSCK-max = <5500>;
59 tDQSCK-max = <5500>;
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300template_wasp_k31.h367 FREQ2FBIN(5500, 0),
392 FREQ2FBIN(5500, 0),
404 FREQ2FBIN(5500, 0),
417 FREQ2FBIN(5500, 0),
498 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
507 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
526 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
533 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0),
553 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
561 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_ap121.h371 FREQ2FBIN(5500, 0),
396 FREQ2FBIN(5500, 0),
409 FREQ2FBIN(5500, 0),
422 FREQ2FBIN(5500, 0),
502 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
511 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
530 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
537 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0),
557 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
565 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_aphrodite.h373 FREQ2FBIN(5500, 0),
398 FREQ2FBIN(5500, 0),
410 FREQ2FBIN(5500, 0),
423 FREQ2FBIN(5500, 0),
504 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
513 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
532 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
539 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0),
559 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
567 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_cus157.h360 FREQ2FBIN(5500, 0),
385 FREQ2FBIN(5500, 0),
398 FREQ2FBIN(5500, 0),
411 FREQ2FBIN(5500, 0),
491 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
500 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
519 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
526 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0),
546 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
554 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_generic.h372 FREQ2FBIN(5500, 0),
397 FREQ2FBIN(5500, 0),
409 FREQ2FBIN(5500, 0),
422 FREQ2FBIN(5500, 0),
503 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
512 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
531 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
538 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0),
558 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
566 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_hb112.h374 FREQ2FBIN(5500, 0),
399 FREQ2FBIN(5500, 0),
412 FREQ2FBIN(5500, 0),
425 FREQ2FBIN(5500, 0),
505 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
514 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
533 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
540 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0),
560 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
568 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_hb116.h375 FREQ2FBIN(5500, 0),
400 FREQ2FBIN(5500, 0),
413 FREQ2FBIN(5500, 0),
426 FREQ2FBIN(5500, 0),
506 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
515 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
534 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
541 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0),
561 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
569 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_osprey_k31.h375 FREQ2FBIN(5500, 0),
400 FREQ2FBIN(5500, 0),
413 FREQ2FBIN(5500, 0),
426 FREQ2FBIN(5500, 0),
506 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
515 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
534 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
541 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0),
561 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
569 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_wasp_2.h372 FREQ2FBIN(5500, 0),
397 FREQ2FBIN(5500, 0),
409 FREQ2FBIN(5500, 0),
422 FREQ2FBIN(5500, 0),
503 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
512 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
531 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
538 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0),
558 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
566 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_xb112.h374 FREQ2FBIN(5500, 0),
399 FREQ2FBIN(5500, 0),
412 FREQ2FBIN(5500, 0),
425 FREQ2FBIN(5500, 0),
505 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
514 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
533 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
540 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0),
560 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
568 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
H A Dar9300template_xb113.h330 …{FREQ2FBIN(5500, 0),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual…
374 FREQ2FBIN(5500, 0),
399 FREQ2FBIN(5500, 0),
412 FREQ2FBIN(5500, 0),
505 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
514 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
533 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
540 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0),
560 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
568 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dmaxim,max77693.yaml41 Valid values: 3300 - 5500, step by 25 (rounded down)
44 maximum: 5500
H A Drichtek,rt8515.yaml61 according to the formula Imax = 5500 / RFS. The lowest
73 according to the formula Imax = 5500 / RTS. The lowest
/freebsd/sys/contrib/device-tree/Bindings/ddr/
H A Dlpddr2.txt73 tDQSCK-max = <5500>;
94 tDQSCK-max = <5500>;
H A Dlpddr2-timings.txt46 tDQSCK-max = <5500>;
/freebsd/share/man/man4/
H A Duslcom.484 Clipsal 5000CT2, 5500PACA, 5500PCU, 560884, 5800PC, C5000CT2
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr2.yaml176 tDQSCK-max = <5500>;
197 tDQSCK-max = <5500>;
H A Dlpddr2-timings.txt46 tDQSCK-max = <5500>;
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood-ns2max.dts40 <5500 8>;
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rt6160-regulator.yaml15 input voltage range from 2200mV to 5500mV.
/freebsd/sys/contrib/dev/rtw89/
H A Dsar.c28 case 5500 ... 5720: in rtw89_sar_get_subband()
297 { .start_freq = 5500, .end_freq = 5720, }, in rtw89_ops_set_sar_specs()
/freebsd/lib/libpmc/
H A Dpmc.corei7uc.331 .Tn Core i7 and Xeon 5500
56 Intel Core i7 and Xeon 5500 PMCs are documented in
64 .Ss COREI7 AND XEON 5500 UNCORE FIXED FUNCTION PMCS
67 .Ss COREI7 AND XEON 5500 UNCORE PROGRAMMABLE PMCS
106 Core i7 and Xeon 5500 uncore programmable PMCs support the following events:

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