5\-bits (full) in projects: freebsd - OpenGrok search results

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Searched +full:5 +full:- +full:bits (Results 1 – 25 of 1017) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A D	HexagonDepInstrFormats.td	`1 //===---------- [all...]`
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A D	MipsMSAInstrFormats.td	`1 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 let Inst{31-26} = 0b011110; 16 let Inst{31-26} = 0b010001; 20 let Inst{31-26} = 0b000000; 30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst { 31 bits<5> ws; 32 bits<5> wd; 33 bits<3> m; [all …]`
H A D	MicroMipsInstrFormats.td	1 //===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -- tablegen ---===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===// 15 //===----------------------------------------------------------------------===// 40 // Base class for MicroMIPS 16-bit instructions. 47 field bits<16> Inst; 48 field bits<16> SoftFail = 0; 49 bits<6> Opcode = 0x0; [all …]
H A D	MicroMips32r6InstrFormats.td	1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -- tablegen --==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 19 //===----------------------------------------------------------------------===// 23 //===----------------------------------------------------------------------===// 31 //===----------------------------------------------------------------------===// 35 //===----------------------------------------------------------------------===// 38 bits<10> offset; 40 bits<16> Inst; [all …]
H A D	MipsDSPInstrFormats.td	1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 23 def HasDSP : Predicate<"Subtarget->hasDSP()">, 25 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">, 27 def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">, 39 class Field6<bits<6> val> { 40 bits<6> V = val; 64 // ADDU.QB sub-class format. 65 class ADDU_QB_FMT<bits<5> op> : DSPInst { [all …]
H A D	MipsInstrFormats.td	1 //===-- MipsInstrFormats.td - Mips Instruction Formats ------ tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 14 // opcode - operation code. 15 // rs - src reg. 16 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 17 // rd - dst reg, only used on 3 regs instr. 18 // shamt - only used on shift instructions, contains the shift amount. 19 // funct - combined with opcode field give us an operation code. [all …]
H A D	MicroMipsDSPInstrFormats.td	`1 //===-- MicroMipsDSPInstrFormats.td - Instruction Formats --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 24 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> { 25 bits<5> rd; 26 bits<5> rs; 27 bits<5> rt; 29 let Inst{31-26} = 0b000000; 30 let Inst{25-21} = rt; 31 let Inst{20-16} = rs; [all …]`
H A D	Mips32r6InstrFormats.td	1 //=- Mips32r6InstrFormats.td - Mips32r6 Instruction Formats -- tablegen --==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 37 //===----------------------------------------------------------------------===// 41 //===----------------------------------------------------------------------===// 43 class OPGROUP<bits<6> Val> { 44 bits<6> Value = Val; 65 class OPCODE2<bits<2> Val> { 66 bits<2> Value = Val; [all …]
H A D	Mips16InstrFormats.td	1 //===- Mips16InstrFormats.td - Mips Instruction Formats ----- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 16 // immediate 4-,5-,8- or 11-bit immediate, branch displacement, or 19 // op 5-bit major operation code 21 // rx 3-bit source or destination register 23 // ry 3-bit source or destination register 25 // rz 3-bit source or destination register 27 // sa 3- or 5-bit shift amount [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A D	CSKYInstrFormats.td	1 //===-- CSKYInstrFormats.td - CSKY Instruction Formats ------ tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 class AddrMode<bits<5> val> { 10 bits<5> Value = val; 18 def AddrMode16H : AddrMode<5>; // ld16.h, +64b 27 field bits<32> SoftFail = 0; 33 let TSFlags{4 - 0} = AM.Value; 42 class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr, 45 field bits<32> Inst; [all …]
H A D	CSKYInstrFormats16Instr.td	`1 //===- CSKYInstrFormats16Instr.td - 16-bit Instr. Formats -- tablegen ---===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 class J16<bits<5> sop, string opstr, dag ins> 12 bits<10> offset; 14 let Inst{14 - 10} = sop; 15 let Inst{9 - 0} = offset; 18 class J16_B<bits<5> sop, string opstr> 21 bits<10> offset; 23 let Inst{14 - 10} = sop; [all …]`
H A D	CSKYInstrFormatsF2.td	1 //===- CSKYInstrFormatsF2.td - CSKY Float2.0 Instr Format --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 20 class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins, 23 bits<5> vry; 24 bits<5> vrx; 25 bits<5> vrz; 27 let Inst{25-21} = vry; 28 let Inst{20-16} = vrx; [all …]
H A D	CSKYInstrFormatsF1.td	1 //===- CSKYInstrFormatsF1.td - CSKY Float1.0 Instr Format --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 17 class F_XYZ_BASE<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> patt… 19 bits<4> vrx; 20 bits<4> vry; 21 bits<4> vrz; 22 let Inst{25 - 21} = {0, vry}; 23 let Inst{20 - 16} = {0, vrx}; [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A D	LoongArchLSXInstrFormats.td	1 // LoongArchLSXInstrFormats.td - LoongArch LSX Instr Formats -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 12 // opcode - operation code. 13 // vd/rd/cd - destination register operand. 14 // {r/v}{j/k} - source register operand. 15 // immN - immediate data operand. 17 //===----------------------------------------------------------------------===// 19 // 1RI13-type [all …]
H A D	LoongArchLASXInstrFormats.td	1 // LoongArchLASXInstrFormats.td - LoongArch LASX Instr Formats - tablegen -*-=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 12 // opcode - operation code. 13 // xd/rd/cd - destination register operand. 14 // {r/x}{j/k} - source register operand. 15 // immN - immediate data operand. 17 //===----------------------------------------------------------------------===// 19 // 1RI13-type [all …]
H A D	LoongArchInstrFormats.td	1 //===- LoongArchInstrFormats.td - LoongArch Instr. Formats -- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 12 // opcode - operation code. 13 // rd - destination register operand. 14 // r{j/k} - source register operand. 15 // immN - immediate data operand. 17 //===----------------------------------------------------------------------===// 22 field bits<32> Inst; [all …]
H A D	LoongArchLBTInstrFormats.td	1 // LoongArchLBTInstrFormats.td - LoongArch LBT Instr Formats -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 12 // opcode - operation code. 13 // rd/sd - destination register operand. 14 // rj/rk/sj - source register operand. 15 // immN/ptr - immediate data operand. 23 //===----------------------------------------------------------------------===// 25 // 1R-type (no outs) [all …]
H A D	LoongArchFloatInstrFormats.td	1 // LoongArchFloatInstrFormats.td - LoongArch FP Instr Formats -- tablegen --// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 10 // Describe LoongArch floating-point instructions format 12 // opcode - operation code. 13 // fd - destination register operand. 14 // {c/f}{j/k/a} - source register operand. 15 // immN - immediate data operand. 17 //===----------------------------------------------------------------------===// [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A D	PPCInstrFormats.td	`1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --- tablegen --=// 5 // SPDX-License-Identifier: Apache-2. [all...]`
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVInstrFormatsV.td	1 //===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file describes the RISC-V V extension instruction formats. 11 //===----------------------------------------------------------------------===// 13 class RISCVVFormat<bits<3> val> { 14 bits<3> Value = val; 25 class RISCVMOP<bits<2> val> { 26 bits<2> Value = val; 38 class RISCVLSUMOP<bits<5> val> { [all …]
H A D	RISCVInstrFormatsC.td	1 //===-- RISCVInstrFormatsC.td - RISC-V C Instruction Formats -- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file describes the RISC-V C extension instruction formats. 11 //===----------------------------------------------------------------------===// 16 field bits<16> Inst; 21 field bits<16> SoftFail = 0; 25 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins, 28 bits<5> rs1; 29 bits<5> rs2; [all …]
H A D	RISCVInstrFormats.td	1 //===-- RISCVInstrFormats.td - RISC-V Instruction Formats --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 12 // description in the RISC-V User-Level ISA specification as closely as 18 // specification describes immediate encoding in terms of bit-slicing 22 // a 21-bit value (where the LSB is always zero), we describe it as an imm20 25 //===----------------------------------------------------------------------===// 29 // definitions must be kept in-sync with RISCVBaseInfo.h. 30 class InstFormat<bits<5> val> { [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A D	ARCInstrFormats.td	1 //===- ARCInstrFormats.td - ARC Instruction Formats --------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 14 field bits<64> Inst; 15 field bits<64> SoftFail = 0; 21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> { 27 "\n return isInt<"#BSz#">(N->getSExtValue());"> { 31 // e.g. s3 field may encode the signed integers values -1 .. 6 [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A D	SparcInstrFormats.td	`1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---- tablegen --===// 5 // SPDX-Licens [all...]`
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A D	ARMInstrFormats.td	1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 15 // ad-hoc solution used to emit machine instruction encodings by our machine 17 class Format<bits<6> val> { 18 bits<6> Value = val; 27 def DPSoRegRegFrm : Format<5>; 76 // UnaryDP - Indicates this is a unary data processing instruction, i.e. 80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into [all …]

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