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/linux/arch/x86/crypto/
H A Dserpent-sse2-i586-asm_32.S3 * Serpent Cipher 4-way parallel algorithm (i586/SSE2)
17 #define arg_ctx 4
23 4-way SSE2 serpent
39 movd (4*(i)+(j))*4(CTX), t; \
42 #define K(x0, x1, x2, x3, x4, i) \ argument
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
69 pxor x2, x3; \
70 pxor x4, x3; \
71 movdqa x3, x4; \
[all …]
H A Dserpent-sse2-x86_64-asm_64.S41 #define S0_1(x0, x1, x2, x3, x4) \ argument
42 movdqa x3, x4; \
43 por x0, x3; \
47 pxor x1, x3; \
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
52 pxor x3, x0; \
56 pxor x2, x3; \
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
64 pxor x3, x0; \
65 pxor RNOT, x3; \
[all …]
/linux/drivers/clk/mmp/
H A Dclk-of-pxa1928.c53 {0, "vctcxo_d4", "vctcxo", 1, 4, 0},
99 …, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
100 …, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock},
101 …, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 4, 3, 0, &uart2_lock},
102 …, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 4, 3, 0, &uart3_lock},
103 …mes, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 4, 3, 0, &ssp0_lock},
104 …mes, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 4, 3, 0, &ssp1_lock},
108 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0…
109 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0…
110 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0…
[all …]
H A Dclk-of-pxa168.c163 …arent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0, 4, 3, 0, &twsi0_lock},
164 …arent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI1, 4, 3, 0, &twsi1_lock},
165 …{0, "kpc_mux", kpc_parent_names, ARRAY_SIZE(kpc_parent_names), CLK_SET_RATE_PARENT, APBC_KPC, 4, 3…
166 …{0, "pwm0_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4,…
167 …{0, "pwm1_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4,…
168 …{0, "pwm2_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM2, 4,…
169 …{0, "pwm3_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM3, 4,…
170 …arent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
171 …arent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
172 …arent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
[all …]
/linux/sound/soc/codecs/
H A Drt1318.h101 #define RT1318_PLLIN_MASK (0x7 << 4)
102 #define RT1318_PLLIN_BCLK0 (0x0 << 4)
103 #define RT1318_PLLIN_BCLK1 (0x1 << 4)
104 #define RT1318_PLLIN_RC (0x2 << 4)
105 #define RT1318_PLLIN_MCLK (0x3 << 4)
106 #define RT1318_PLLIN_SDW1 (0x4 << 4)
107 #define RT1318_PLLIN_SDW2 (0x5 << 4)
108 #define RT1318_PLLIN_SDW3 (0x6 << 4)
109 #define RT1318_PLLIN_SDW4 (0x7 << 4)
114 #define RT1318_SYSCLK_PLL2B (0x3 << 0)
[all …]
H A Drt5677.h354 #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
363 #define RT5677_SLB_ADC4_MASK (0x3 << 6)
365 #define RT5677_SLB_ADC3_MASK (0x3 << 4)
366 #define RT5677_SLB_ADC3_SFT 4
367 #define RT5677_SLB_ADC2_MASK (0x3 << 2)
369 #define RT5677_SLB_ADC1_MASK (0x3 << 0)
389 #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
390 #define RT5677_ANA_DAC3_SRC_SEL_SFT 4
391 #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
394 /* IF/DSP to DAC3/4 Mixer Control (0x16) */
[all …]
H A Drk3308_codec.h24 #define RK3308_ADC_DIG_OFFSET(ch) (((ch) & 0x3) * 0xc0 + 0x0)
79 #define RK3308_ADC_ANA_OFFSET(ch) (((ch) & 0x3) * 0x40 + 0x340)
116 #define RK3308_DAC_MCLK_GATING BIT(4)
124 #define RK3308_ADC_I2S_VALID_LEN_MSK (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT)
125 #define RK3308_ADC_I2S_VALID_LEN_32BITS (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT)
130 #define RK3308_ADC_I2S_MODE_MSK (0x3 << RK3308_ADC_I2S_MODE_SFT)
131 #define RK3308_ADC_I2S_MODE_PCM (0x3 << RK3308_ADC_I2S_MODE_SFT)
140 #define RK3308_ADC_MODE_MASTER BIT(4)
142 #define RK3308_ADC_I2S_FRAME_LEN_MSK (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT)
143 #define RK3308_ADC_I2S_FRAME_32BITS (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT)
[all …]
H A Dmt6359.h272 #define RG_AUDACCDETVTHACAL_SFT 4
274 #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
308 #define RG_AUDMICBIAS1VREF_SFT 4
310 #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)
441 #define RG_EINT0INVEN_SFT 4
443 #define RG_EINT0INVEN_MASK_SFT (0x1 << 4)
499 #define ACCDET_ANA_MAJOR_REV_SFT 4
501 #define ACCDET_ANA_MAJOR_REV_MASK_SFT (0xF << 4)
515 #define ACCDET_DSN_CBS_MASK 0x3
516 #define ACCDET_DSN_CBS_MASK_SFT (0x3 << 0)
[all …]
H A Drt5668.h406 #define RT5668_MB2_PATH_MASK (0x1 << 4)
407 #define RT5668_CTRL_MB2_REG (0x1 << 4)
408 #define RT5668_CTRL_MB2_FSM (0x0 << 4)
420 #define RT5668_EXT_JD_SRC (0x7 << 4)
421 #define RT5668_EXT_JD_SRC_SFT 4
422 #define RT5668_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
423 #define RT5668_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
424 #define RT5668_EXT_JD_SRC_JDH (0x2 << 4)
425 #define RT5668_EXT_JD_SRC_JDL (0x3 << 4)
426 #define RT5668_EXT_JD_SRC_MANUAL (0x4 << 4)
[all …]
H A Drt5682s.h453 #define RT5682S_SEL_FAST_OFF_MASK (0x3 << 9)
468 #define RT5682S_MB2_PATH_BIT 4
469 #define RT5682S_MB2_PATH_MASK (0x1 << 4)
470 #define RT5682S_CTRL_MB2_REG (0x1 << 4)
471 #define RT5682S_CTRL_MB2_FSM (0x0 << 4)
492 #define RT5682S_EXT_JD_SRC (0x7 << 4)
493 #define RT5682S_EXT_JD_SRC_SFT 4
494 #define RT5682S_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
495 #define RT5682S_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
496 #define RT5682S_EXT_JD_SRC_JDH (0x2 << 4)
[all …]
H A Dtscs454.h18 #define R_IRQMASK VIRT_ADDR(0x0, 0x3)
70 #define R_HSDSTAT VIRT_ADDR(0x1, 0x3)
102 #define R_SUBCTL VIRT_ADDR(0x2, 0x3)
126 #define R_SPKEQFILT VIRT_ADDR(0x3, 0x1)
127 #define R_SPKCRWDL VIRT_ADDR(0x3, 0x2)
128 #define R_SPKCRWDM VIRT_ADDR(0x3, 0x3)
129 #define R_SPKCRWDH VIRT_ADDR(0x3, 0x4)
130 #define R_SPKCRRDL VIRT_ADDR(0x3, 0x5)
131 #define R_SPKCRRDM VIRT_ADDR(0x3, 0x6)
132 #define R_SPKCRRDH VIRT_ADDR(0x3, 0x7)
[all …]
H A Dnau8325.h62 #define NAU8325_CLK_DAC_SRC_MASK (0x3 << NAU8325_CLK_DAC_SRC_SFT)
64 #define NAU8325_CLK_MUL_SRC_MASK (0x3 << NAU8325_CLK_MUL_SRC_SFT)
84 #define NAU8325_OCP_OTP_SHTDWN_INT_SFT 4
135 #define NAU8325_DACCM_CTL_MASK (0x3 << NAU8325_DACCM_CTL_SFT)
148 #define NAU8325_I2S_DL_MASK (0x3 << NAU8325_I2S_DL_SFT)
149 #define NAU8325_I2S_DL_32 (0x3 << NAU8325_I2S_DL_SFT)
153 #define NAU8325_I2S_DF_MASK 0x3
157 #define NAU8325_I2S_DF_PCM_AB 0x3
187 #define NAU8325_UNMUTE_CTL_MASK (0x3 << NAU8325_UNMUTE_CTL_SFT)
188 #define NAU8325_ANA_MUTE_SFT 4
[all …]
H A Drt5651.h261 #define RT5651_ADC_L_BST_MASK (0x3 << 14)
263 #define RT5651_ADC_R_BST_MASK (0x3 << 12)
265 #define RT5651_ADC_COMP_MASK (0x3 << 10)
303 #define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
304 #define RT5651_STO2_ADC_R1_SRC_SFT 4
305 #define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
306 #define RT5651_STO2_ADC_R1_SRC_DACMIXR (0x0 << 4)
339 #define RT5651_M_DAC_R2_MIXR (0x1 << 4)
340 #define RT5651_M_DAC_R2_MIXR_SFT 4
365 #define RT5651_M_STO_DD_R2 (0x1 << 4)
[all …]
H A Drt5631.h145 #define RT5631_M_MONO_IN_TO_RECMIXER_R (0x1 << 4)
146 #define RT5631_M_MONO_IN_RECMIXR_BIT 4
216 #define RT5631_MIC1_BOOST_CTRL_30DB (0x3 << 12)
228 #define RT5631_MIC2_BOOST_CTRL_30DB (0x3 << 8)
244 #define RT5631_MICBIAS1_SHORT_CURR_DET_MASK (0x3 << 4)
245 #define RT5631_MICBIAS1_SHORT_CURR_DET_600UA (0x0 << 4)
246 #define RT5631_MICBIAS1_SHORT_CURR_DET_1500UA (0x1 << 4)
247 #define RT5631_MICBIAS1_SHORT_CURR_DET_2000UA (0x2 << 4)
257 #define RT5631_MICBIAS2_SHORT_CURR_DET_MASK (0x3)
280 #define RT5631_DMIC_CLK_CTRL_MASK (0x3 << 4)
[all …]
H A Drt5640.h197 #define RT5640_ID_MASK (0x3 << 1)
200 #define RT5640_ID_5642 (0x3 << 1)
257 #define RT5640_ADC_L_BST_MASK (0x3 << 14)
259 #define RT5640_ADC_R_BST_MASK (0x3 << 12)
261 #define RT5640_ADC_COMP_MASK (0x3 << 10)
273 #define RT5640_ADC_2_SRC_MASK (0x3 << 10)
292 #define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10)
301 #define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4)
302 #define RT5640_MONO_ADC_R1_SRC_SFT 4
303 #define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
[all …]
H A Drt5665.h498 #define RT5665_MB2_PATH_MASK (0x1 << 4)
499 #define RT5665_CTRL_MB2_REG (0x1 << 4)
500 #define RT5665_CTRL_MB2_FSM (0x0 << 4)
506 #define RT5665_EXT_JD_SRC (0x7 << 4)
507 #define RT5665_EXT_JD_SRC_SFT 4
508 #define RT5665_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
509 #define RT5665_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
510 #define RT5665_EXT_JD_SRC_JD1_1 (0x2 << 4)
511 #define RT5665_EXT_JD_SRC_JD1_2 (0x3 << 4)
512 #define RT5665_EXT_JD_SRC_JD2 (0x4 << 4)
[all …]
H A Drt5616.h218 #define RT5616_ADC_L_BST_MASK (0x3 << 14)
220 #define RT5616_ADC_R_BST_MASK (0x3 << 12)
222 #define RT5616_ADC_COMP_MASK (0x3 << 10)
276 #define RT5616_M_STO_DD_R2 (0x1 << 4)
277 #define RT5616_M_STO_DD_R2_SFT 4
314 #define RT5616_DAC_L2_SEL_MASK (0x3 << 14)
319 #define RT5616_DAC_L2_SEL_BASS (0x3 << 14)
320 #define RT5616_DAC_R2_SEL_MASK (0x3 << 12)
333 #define RT5616_RXDC_SEL_MASK (0x3 << 8)
338 #define RT5616_RXDC_SEL_SWAP (0x3 << 8)
[all …]
H A Dda7219.h158 #define DA7219_MIC_1_AMP_IN_SEL_MASK (0x3 << 0)
191 #define DA7219_CIF_I2C_ADDR_CFG_MASK (0x3 << 0)
199 #define DA7219_PLL_INDIV_18_TO_36_MHZ (0x3 << 2)
204 #define DA7219_PLL_MODE_MASK (0x3 << 6)
224 #define DA7219_PLL_SRM_STATUS_SHIFT 4
225 #define DA7219_PLL_SRM_STATUS_MASK (0xF << 4)
226 #define DA7219_PLL_SRM_STS_MCLK (0x1 << 4)
231 #define DA7219_DAI_L_SRC_MASK (0x3 << 0)
232 #define DA7219_DAI_R_SRC_SHIFT 4
233 #define DA7219_DAI_R_SRC_MASK (0x3 << 4)
[all …]
/linux/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h26 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30)
30 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30)
31 #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28)
35 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26)
39 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26)
40 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
41 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
42 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
43 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
44 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
[all …]
/linux/include/linux/qed/
H A Dfcoe_common.h19 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
26 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
161 #define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
169 #define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
171 #define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
173 #define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
174 #define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
189 #define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
217 #define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
229 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dcnic_defs.h17 #define L2_KWQE_OPCODE_VALUE_FLUSH (4)
63 #define L4_KCQE_COMPLETION_STATUS_NIC_ERROR (4)
73 #define L4_LAYER_CODE (4)
98 #define L4_KCQ_LAYER_CODE (0x7<<4)
99 #define L4_KCQ_LAYER_CODE_SHIFT 4
112 #define L4_KCQ_LAYER_CODE (0x7<<4)
113 #define L4_KCQ_LAYER_CODE_SHIFT 4
137 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4)
138 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4
149 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4)
[all …]
/linux/arch/arm/mach-omap2/
H A Dprm-regbits-33xx.h13 #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
15 #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
19 #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
21 #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
23 #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
28 #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
29 #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
30 #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
32 #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
33 #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dni_reg.h30 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0)
35 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)
38 # define NI_GRPH_PRESCALE_BYPASS (1 << 4)
41 # define NI_OVL_PRESCALE_BYPASS (1 << 4)
44 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0)
48 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4)
56 # define NI_OUTPUT_CSC_PROG_COEFF 4
58 # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4)
61 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0)
65 # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4)
[all …]
/linux/drivers/scsi/bnx2i/
H A D57xx_iscsi_hsi.h124 #define ISCSI_CLEANUP_REQUEST_TYPE (0x3<<14)
130 #define ISCSI_CLEANUP_REQUEST_TYPE (0x3<<14)
177 #define ISCSI_CLEANUP_RESPONSE_TYPE (0x3<<14)
183 #define ISCSI_CLEANUP_RESPONSE_TYPE (0x3<<14)
200 #define ISCSI_CMD_REQUEST_RESERVED1 (0x3<<3)
214 #define ISCSI_CMD_REQUEST_RESERVED1 (0x3<<3)
237 #define ISCSI_CMD_REQUEST_TYPE (0x3<<14)
243 #define ISCSI_CMD_REQUEST_TYPE (0x3<<14)
250 u32 cdb[4];
317 #define ISCSI_CMD_RESPONSE_BR_RESIDUAL_OVERFLOW (0x1<<4)
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-reg.h93 #define DL1_ON_SFT 4
95 #define DL1_ON_MASK_SFT (0x1 << 4)
494 #define GAIN1_MODE_SFT 4
496 #define GAIN1_MODE_MASK_SFT (0xf << 4)
510 #define GAIN2_MODE_SFT 4
512 #define GAIN2_MODE_MASK_SFT (0xf << 4)
582 #define PCM_WLEN_MASK 0x3
583 #define PCM_WLEN_MASK_SFT (0x3 << 14)
600 #define PCM_MODE_MASK 0x3
601 #define PCM_MODE_MASK_SFT (0x3 << 3)
[all …]

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