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/linux/drivers/media/dvb-frontends/
H A Dlgs8gxx.h21 #define LGS8GXX_PROD_LGS8G52 4
61 /*0: 0.8Vpp, 1: 1.0Vpp, 2: 1.6Vpp, 3: 2.0Vpp*/
H A Dstv090x.h45 STV090x_RPTLEVEL_16 = 4,
76 enum stv090x_adc_range adc1_range; /* default: 2Vpp */
77 enum stv090x_adc_range adc2_range; /* default: 2Vpp */
/linux/drivers/mtd/maps/
H A Dpcmciamtd.c38 int vpp; member
54 /* Force Vpp */
55 static int vpp; variable
57 /* Set Vpp */
73 MODULE_PARM_DESC(setvpp, "Set Vpp (0=Never, 1=On writes, 2=Always on, default=0)");
74 module_param(vpp, int, 0);
75 MODULE_PARM_DESC(vpp, "Vpp value in 1/10ths eg 33=3.3V 120=12V (Dangerous)");
304 pr_debug("dev = %p on = %d vpp = %d\n\n", dev, on, dev->vpp); in pcmciamtd_set_vpp()
308 pcmcia_fixup_vpp(link, dev->vpp); in pcmciamtd_set_vpp()
420 for (i = 0; i < 4; i++) { in card_settings()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dtwl6030.dtsi44 vpp: regulator-vpp { label
45 compatible = "ti,twl6030-vpp";
85 interrupts = <4>, <10>;
/linux/Documentation/devicetree/bindings/iommu/
H A Dmediatek,iommu.yaml15 pagetable, and only supports 4K size page mapping. Generation two uses the
83 - mediatek,mt8188-iommu-vpp # generation two
90 - mediatek,mt8195-iommu-vpp # generation two
170 - mediatek,mt8188-iommu-vpp
174 - mediatek,mt8195-iommu-vpp
187 - mediatek,mt8188-iommu-vpp
191 - mediatek,mt8195-iommu-vpp
/linux/drivers/pcmcia/
H A Ddb1xxx_ss.c20 * at STATUS[5:4] (instead of STATUS[1:0]).
237 * bits[2:3] set vpp for card
238 * bit 4: enable data buffers
269 switch (state->Vpp) { in db1x_pcmcia_configure()
280 printk(KERN_INFO "pcmcia%d unsupported Vpp %d\n", in db1x_pcmcia_configure()
281 sock->nr, state->Vpp); in db1x_pcmcia_configure()
284 /* sanity check: Vpp must be 0, 12, or Vcc */ in db1x_pcmcia_configure()
285 if (((state->Vcc == 33) && (state->Vpp == 50)) || in db1x_pcmcia_configure()
286 ((state->Vcc == 50) && (state->Vpp == 33))) { in db1x_pcmcia_configure()
287 printk(KERN_INFO "pcmcia%d bad Vcc/Vpp combo (%d %d)\n", in db1x_pcmcia_configure()
[all …]
H A Dpd6729.c355 switch (state->Vpp) { in pd6729_set_socket()
357 dev_dbg(&sock->dev, "not setting Vpp on socket %i\n", in pd6729_set_socket()
362 dev_dbg(&sock->dev, "setting Vpp to Vcc for socket %i\n", in pd6729_set_socket()
367 dev_dbg(&sock->dev, "setting Vpp to 12.0\n"); in pd6729_set_socket()
372 "invalid VPP power value: %i\n", state->Vpp); in pd6729_set_socket()
476 if (map > 4) { in pd6729_set_mem_map()
H A Dsoc_common.c103 r == &skt->vcc ? "Vcc" : "Vpp", in soc_pcmcia_regulator_set()
434 debug(skt, 4, "entering PCMCIA monitoring thread\n"); in soc_common_check_status()
447 debug(skt, 4, "events: %s%s%s%s%s%s\n", in soc_common_check_status()
464 debug(skt, 4, "polling for events\n"); in soc_common_pcmcia_poll_event()
531 debug(skt, 2, "mask: %s%s%s%s%s%s flags: %s%s%s%s%s%s Vcc %d Vpp %d irq %d\n", in soc_common_pcmcia_set_socket()
544 state->Vcc, state->Vpp, state->io_irq); in soc_common_pcmcia_set_socket()
720 p += sprintf(p, "Vpp : %d\n", skt->cs_state.Vpp); in show_status()
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-common.yaml42 - mediatek,mt8188-smi-common-vpp
45 - mediatek,mt8195-smi-common-vpp
75 maxItems: 4
137 - mediatek,mt8195-smi-common-vpp
143 minItems: 4
144 maxItems: 4
/linux/arch/arm/mach-sa1100/
H A Dh3xxx.c45 static void h3xxx_set_vpp(int vpp) in h3xxx_set_vpp() argument
47 gpio_set_value(H3XXX_EGPIO_VPP_ON, vpp); in h3xxx_set_vpp()
52 int err = gpio_request(H3XXX_EGPIO_VPP_ON, "Flash Vpp"); in h3xxx_flash_init()
251 }, { /* static memory bank 4 CS#4 */
H A Djornada720.c82 {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
102 {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
341 static void jornada720_set_vpp(int vpp) in jornada720_set_vpp() argument
343 if (vpp) in jornada720_set_vpp()
/linux/include/linux/mtd/
H A Dpfow.h73 #define DSR_VPPS (1<<3) /* RC; 0-Vpp OK, * 1-Vpp low */
74 #define DSR_PROGRAM_STATUS (1<<4) /* RC; 0-successful, 1-error */
/linux/include/dt-bindings/memory/
H A Dmediatek,mt8188-memory-port.h21 #define SMI_L4_ID 4
46 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
49 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
54 * disp 0 ~ 4G larb0/1/2/3
55 * vcodec 4G ~ 8G larb19(21)[1]/21(22)/23
63 * iommu-vpp: larb1/3/4/6/7/11B/12/14/15/16A/17A/23/27
74 #define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(SMI_L0_ID, 4)
83 #define M4U_PORT_L1_DISP_OVL1_HDR MTK_M4U_ID(SMI_L1_ID, 4)
92 #define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(SMI_L2_ID, 4)
99 #define M4U_PORT_L3_HDR_DS_SMI MTK_M4U_ID(SMI_L3_ID, 4)
[all …]
/linux/include/pcmcia/
H A Dds.h108 unsigned int vpp; member
123 u16 _win:4;
135 u16 reserved:4;
141 char *prod_id[4];
267 #define CONF_AUTO_SET_VPP 0x0200 /* set Vpp? */
H A Dsoc_common.h63 #define SOC_STAT_VS1 4 /* Voltage sense 1 */
69 struct soc_pcmcia_regulator vpp; member
H A Dss.h53 u_char Vcc, Vpp; member
109 #define MAX_WIN 4
/linux/Documentation/pcmcia/
H A Ddriver-changes.rst15 - CONF_AUTO_SET_VPP : set Vpp
24 config_index, config_base, vpp.
28 `struct pcmcia_device *p_dev->resource[2,3,4,5]` for up to four ioport
/linux/Documentation/admin-guide/perf/
H A Dmeson-ddr-pmu.rst8 The monitor includes 4 channels. Each channel can count the request accessing
20 meson_ddr_bw/chan_{1,2,3,4}_rw_bytes/ events are channel-specific events.
27 + vpu_read1 - from OSD + VPP read
/linux/drivers/mtd/chips/
H A Dcfi_probe.c223 for (i=0; i<(sizeof(struct cfi_ident) + num_erase_regions * 4); i++) in cfi_chip_setup()
361 printk("Vcc Minimum: %2d.%d V\n", cfip->VccMin >> 4, cfip->VccMin & 0xf); in print_cfi_ident()
362 printk("Vcc Maximum: %2d.%d V\n", cfip->VccMax >> 4, cfip->VccMax & 0xf); in print_cfi_ident()
364 printk("Vpp Minimum: %2d.%d V\n", cfip->VppMin >> 4, cfip->VppMin & 0xf); in print_cfi_ident()
365 printk("Vpp Maximum: %2d.%d V\n", cfip->VppMax >> 4, cfip->VppMax & 0xf); in print_cfi_ident()
368 printk("No Vpp line\n"); in print_cfi_ident()
/linux/include/linux/
H A Dfsl_devices.h52 FSL_USB_VER_2_5 = 4,
132 #define SPI_QE (1 << 4) /* SPI unit is in QE block */
141 int(*voltage_set)(int slot, int vcc, int vpp);
/linux/drivers/gpu/drm/meson/
H A Dmeson_vpp.c18 * VPP Handles all the Post Processing after the Scanout from the VIU
115 writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4), in meson_vpp_init()
146 writel_relaxed(VPP_VSC_BANK_LENGTH(4) | VPP_HSC_BANK_LENGTH(4) | in meson_vpp_init()
/linux/drivers/regulator/
H A Dtwl6030-regulator.c52 #define VREG_VOLTAGE_SMPS 4
57 #define VREG_BC_CLK_RST 4
594 TWL6030_ADJUSTABLE_LDO(VPP, 0x6c);
653 TWL6030_OF_MATCH("ti,twl6030-vpp", VPP),
750 * - SC_DETECT1 (vintana2, vmmc1/2, vaux1/2/3/4) in twlreg_probe()
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_cfg_data.c19 MT8183_MDP_COMP_ISP_IMGI, /* 4 */
58 MT8188_MDP_COMP_RDMA2, /* 4 */
105 MT8195_MDP_COMP_CAMIN, /* 4 */
176 [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8188-vpp-mutex" },
177 [MDP_INFRA_MUTEX2] = { .compatible = "mediatek,mt8188-vpp-mutex" },
183 [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8195-vpp-mutex" },
184 [MDP_INFRA_MUTEX2] = { .compatible = "mediatek,mt8195-vpp-mutex" },
203 .rdma_event_num = 4,
207 .wrot_event_num = 4,
323 {0, 0, 4}
[all …]
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dfw_qos.c40 /* allocate vpp opcode modifiers */
52 u8 prio2tc[4];
58 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
77 __be32 reserved1[4];
100 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1]; in mlx4_SET_PORT_PRIO2TC()
/linux/drivers/clk/berlin/
H A Dbg2q.c66 .vcodiv = {1, 0, 2, 0, 3, 4, 0, 6, 8},
87 BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4),
128 BERLIN2_DIV_GATE(REG_CLKENABLE, 4),
214 .name = "vpp",

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