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/linux/arch/arm64/crypto/
H A Dsm4-ce-asm.h12 sm4e b0.4s, v24.4s; \
13 sm4e b0.4s, v25.4s; \
14 sm4e b0.4s, v26.4s; \
15 sm4e b0.4s, v27.4s; \
16 sm4e b0.4s, v28.4s; \
17 sm4e b0.4s, v29.4s; \
18 sm4e b0.4s, v30.4s; \
19 sm4e b0.4s, v31.4s; \
20 rev64 b0.4s, b0.4s; \
29 sm4e b0.4s, v24.4s; \
[all …]
H A Dsm4-neon-core.S41 zip1 RTMP0.4s, s0.4s, s1.4s; \
42 zip1 RTMP1.4s, s2.4s, s3.4s; \
43 zip2 RTMP2.4s, s0.4s, s1.4s; \
44 zip2 RTMP3.4s, s2.4s, s3.4s; \
51 zip1 RTMP0.4s, s0.4s, s1.4s; \
52 zip1 RTMP1.4s, s2.4s, s3.4s; \
53 zip2 RTMP2.4s, s0.4s, s1.4s; \
54 zip2 RTMP3.4s, s2.4s, s3.4s; \
55 zip1 RTMP4.4s, s4.4s, s5.4s; \
56 zip1 RTMP5.4s, s6.4s, s7.4s; \
[all …]
H A Dsm4-ce-cipher-core.S6 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8
7 .set .Lv\b\().4s, \b
19 ld1 {v8.4s}, [x2]
20 ld1 {v0.4s-v3.4s}, [x0], #64
22 ld1 {v4.4s-v7.4s}, [x0]
23 sm4e v8.4s, v0.4s
24 sm4e v8.4s, v1.4s
25 sm4e v8.4s, v2.4s
26 sm4e v8.4s, v3.4s
27 sm4e v8.4s, v4.4s
[all …]
H A Dsm4-ce-gcm-core.S19 .set .Lv\b\().4s, \b
112 sm4e b0.4s, v24.4s; \
114 sm4e b0.4s, v25.4s; \
116 sm4e b0.4s, v26.4s; \
118 sm4e b0.4s, v27.4s; \
120 sm4e b0.4s, v28.4s; \
122 sm4e b0.4s, v29.4s; \
124 sm4e b0.4s, v30.4s; \
126 sm4e b0.4s, v31.4s; \
128 rev64 b0.4s, b0.4s; \
[all …]
/linux/arch/arm64/kernel/vdso/
H A Dvgetrandom-chacha.S52 ld1 { copy1.4s, copy2.4s }, [x1]
54 ld1 { copy3.2s }, [x2]
56 movi one_v.2s, #1
57 uzp1 one_v.4s, one_v.4s, one_v.4s
76 add state0.4s, state0.4s, state1.4s
81 add state2.4s, state2.4s, state3.4s
83 shl state1.4s, tmp.4s, #12
84 sri state1.4s, tmp.4s, #20
87 add state0.4s, state0.4s, state1.4s
89 shl state3.4s, tmp.4s, #8
[all …]
/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]
/linux/lib/crypto/powerpc/
H A Dchacha-p10le-8x.S14 # 4. c += d; b ^= c; b <<<= 7
21 # 4 blocks (a b c d)
195 vadduwm 0, 0, 4
221 vxor 4, 4, 8
232 vrlw 4, 4, 25 #
241 vadduwm 0, 0, 4
271 vxor 4, 4, 8
279 vrlw 4, 4, 28 #
295 vadduwm 3, 3, 4
322 vxor 4, 4, 9
[all …]
/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
[all …]
/linux/drivers/watchdog/
H A Dsbc8360.c76 * MOV AX,000nH (set multiplier n, from 1-4)
95 * M | 1 2 3 4
97 * 0 | 0.5s 5s 50s 100s
98 * 1 | 1s 10s 100s 200s
99 * 2 | 1.5s 15s 150s 300s
100 * 3 | 2s 20s 200s 400s
101 * 4 | 2.5s 25s 250s 500s
102 * 5 | 3s 30s 300s 600s
103 * 6 | 3.5s 35s 350s 700s
104 * 7 | 4s 40s 400s 800s
[all …]
/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dtie.h2 * This header file describes this specific Xtensa processor's TIE extensions
46 #define XCHAL_NCP_SA_ALIGN 4
50 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
57 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
60 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
82 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
93 #define XCHAL_NCP_SA_LIST(s) \ argument
94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]
/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dtie.h2 * This header file describes this specific Xtensa processor's TIE extensions
45 #define XCHAL_NCP_SA_ALIGN 4
56 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
59 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
81 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
92 #define XCHAL_NCP_SA_LIST(s) \ argument
93 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
98 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
[all …]
/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
65 #define XCHAL_NCP_SA_ALIGN 4
69 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
76 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
79 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
101 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
112 #define XCHAL_NCP_SA_LIST(s) \ argument
113 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
[all …]
/linux/Documentation/driver-api/mtd/
H A Dspi-nor.rst14 flash's parameters and settings. If the flash defines the SFDP tables
15 it's likely that you won't need a flash entry at all, and instead
30 Do all the tests from below and paste them in the commit's comments
81 1S-1S-1S
85 1S-1S-1S (fast read)
89 1S-1S-2S
93 1S-2S-2S
95 mode cycles 4
97 1S-1S-4S
101 1S-4S-4S
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pko-defs.h99 } s; member
112 } s; member
129 } s; member
137 uint64_t back:4;
145 uint64_t back:4;
148 } s; member
159 } s; member
193 uint64_t back:4;
201 uint64_t back:4;
204 } s; member
[all …]
H A Dcvmx-lmcx-defs.h191 } s; member
216 } s; member
256 } s; member
282 } s; member
295 } s; member
306 } s; member
319 } s; member
352 } s; member
360 uint64_t nctl_csr:4;
361 uint64_t nctl_clk:4;
[all …]
H A Dcvmx-asxx-defs.h70 } s; member
83 } s; member
91 uint64_t txpsh:4;
92 uint64_t txpop:4;
93 uint64_t ovrflw:4;
95 uint64_t ovrflw:4;
96 uint64_t txpop:4;
97 uint64_t txpsh:4;
100 } s; member
125 uint64_t txpsh:4;
[all …]
H A Dcvmx-pip-defs.h162 } s; member
181 } s; member
194 } s; member
244 } s; member
285 } s; member
318 } s; member
328 uint64_t grp:4;
338 uint64_t grp:4;
360 } s; member
375 } s; member
[all …]
H A Dcvmx-sriox-defs.h101 } s; member
129 } s; member
144 } s; member
163 } s; member
179 uint64_t obulk:4;
180 uint64_t optrs:4;
200 uint64_t optrs:4;
201 uint64_t obulk:4;
212 } s; member
223 uint64_t obulk:4;
[all …]
/linux/arch/loongarch/kvm/intc/
H A Deiointc.c10 static void eiointc_set_sw_coreisr(struct loongarch_eiointc *s) in eiointc_set_sw_coreisr() argument
16 ipnum = (s->ipmap >> (irq / 32 * 8)) & 0xff; in eiointc_set_sw_coreisr()
17 if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) { in eiointc_set_sw_coreisr()
19 ipnum = ipnum < 4 ? ipnum : 0; in eiointc_set_sw_coreisr()
22 cpuid = ((u8 *)s->coremap)[irq]; in eiointc_set_sw_coreisr()
23 vcpu = kvm_get_vcpu_by_cpuid(s->kvm, cpuid); in eiointc_set_sw_coreisr()
28 if (test_bit(irq, (unsigned long *)s->coreisr[cpu])) in eiointc_set_sw_coreisr()
29 __set_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
31 __clear_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
35 static void eiointc_update_irq(struct loongarch_eiointc *s, int irq, int level) in eiointc_update_irq() argument
[all …]
/linux/arch/xtensa/variants/csp/include/variant/
H A Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
65 #define XCHAL_NCP_SA_ALIGN 4
69 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
76 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
79 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
101 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
112 #define XCHAL_NCP_SA_LIST(s) \ argument
113 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
[all …]
/linux/drivers/comedi/drivers/
H A Dadl_pci8164.c11 * Description: Driver for the Adlink PCI-8164 4 Axes Motion Control board
31 struct comedi_subdevice *s, in adl_pci8164_insn_read() argument
35 unsigned long offset = (unsigned long)s->private; in adl_pci8164_insn_read()
46 struct comedi_subdevice *s, in adl_pci8164_insn_write() argument
50 unsigned long offset = (unsigned long)s->private; in adl_pci8164_insn_write()
64 struct comedi_subdevice *s; in adl_pci8164_auto_attach() local
72 ret = comedi_alloc_subdevices(dev, 4); in adl_pci8164_auto_attach()
77 s = &dev->subdevices[0]; in adl_pci8164_auto_attach()
78 s->type = COMEDI_SUBD_PROC; in adl_pci8164_auto_attach()
79 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; in adl_pci8164_auto_attach()
[all …]
H A Ddt3000.c27 * The DT3000 series is Data Translation's attempt to make a PCI
51 #define DPR_DAC_BUFFER (4 * 0x000)
52 #define DPR_ADC_BUFFER (4 * 0x800)
53 #define DPR_COMMAND (4 * 0xfd3)
54 #define DPR_SUBSYS (4 * 0xfd3)
59 #define DPR_SUBSYS_MEM 4
61 #define DPR_ENCODE (4 * 0xfd4)
62 #define DPR_PARAMS(x) (4 * (0xfd5 + (x)))
63 #define DPR_TICK_REG_LO (4 * 0xff5)
64 #define DPR_TICK_REG_HI (4 * 0xff6)
[all …]
/linux/arch/xtensa/variants/de212/include/variant/
H A Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
42 #define XCHAL_NCP_SA_ALIGN 4
46 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
53 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
56 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
78 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
89 #define XCHAL_NCP_SA_LIST(s) \ argument
90 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
91 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
92 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
[all …]
/linux/lib/xz/
H A Dxz_dec_bcj.c21 BCJ_X86 = 4, /* x86 or x86-64 */
67 * x86 1 4
68 * PowerPC 4 0
70 * ARM 4 0
72 * SPARC 4 0
88 static size_t bcj_x86(struct xz_dec_bcj *s, uint8_t *buf, size_t size) in bcj_x86() argument
97 uint32_t prev_mask = s->x86_prev_mask; in bcj_x86()
103 if (size <= 4) in bcj_x86()
106 size -= 4; in bcj_x86()
117 b = buf[i + 4 - mask_to_bit_num[prev_mask]]; in bcj_x86()
[all …]
/linux/tools/testing/selftests/bpf/
H A Ddisasm.c74 [BPF_ADD >> 4] = "+=",
75 [BPF_SUB >> 4] = "-=",
76 [BPF_MUL >> 4] = "*=",
77 [BPF_DIV >> 4] = "/=",
78 [BPF_OR >> 4] = "|=",
79 [BPF_AND >> 4] = "&=",
80 [BPF_LSH >> 4] = "<<=",
81 [BPF_RSH >> 4] = ">>=",
82 [BPF_NEG >> 4] = "neg",
83 [BPF_MOD >> 4]
[all...]

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