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/linux/arch/riscv/kernel/
H A Dkexec_relocate.S24 mv s0, a0
25 mv s1, a1
26 mv s2, a2
27 mv s3, a3
28 mv s4, a4
29 mv s5, zero
30 mv s6, zero
80 j 4f
100 4:
102 mv a0, s3
[all …]
H A Dmcount.S29 addi sp, sp, -4*SZREG
34 addi s0, sp, 4*SZREG
48 addi sp, sp, 4*SZREG
74 mv a0, sp
76 mv a2, a0
107 mv a1, ra
123 mv a0, ra
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_aldebaran.h33 #define NUM_UCLK_DPM_LEVELS 4
35 #define NUM_XGMI_DPM_LEVELS 4
42 #define FEATURE_DPM_FCLK_BIT 4
115 #define THROTTLER_TDC_HBM_BIT 4
292 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
293 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
342 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed]
343 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed]
344 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed]
347 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed]
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h45 #define NUM_UCLK_DPM_LEVELS 4
50 #define NUM_XGMI_PSTATE_LEVELS 4
80 #define FEATURE_DPM_FCLK_BIT 4
199 #define THROTTLER_TEMP_VR_GFX_BIT 4
223 #define FW_DSTATE_SMN_DS_BIT 4
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
633 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
636 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2)
646 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
647 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
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H A Dsmu11_driver_if_arcturus.h32 #define PPTABLE_ARCTURUS_SMU_VERSION 4
39 #define NUM_UCLK_DPM_LEVELS 4
42 #define NUM_XGMI_PSTATE_LEVELS 4
60 #define FEATURE_DPM_FCLK_BIT 4
191 #define THROTTLER_TEMP_VR_GFX_BIT 4
216 #define WORKLOAD_PPLIB_CUSTOM_BIT 4
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
449 XGMI_LINK_WIDTH_4 = 4, // x4
497 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
504 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
[all …]
H A Dsmu11_driver_if_navi10.h45 #define NUM_UCLK_DPM_LEVELS 4
75 #define FEATURE_DPM_SOCCLK_BIT 4
178 #define THROTTLER_TEMP_VR_GFX_BIT 4
201 #define FW_DSTATE_SMN_DS_BIT 4
558 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
559 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
569 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
570 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
574 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
575 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
[all …]
H A Dsmu13_driver_if_v13_0_7.h43 #define NUM_UCLK_DPM_LEVELS 4
53 #define FEATURE_DPM_FCLK_BIT 4
191 #define THROTTLER_TEMP_MEM_BIT 4
216 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4
734 uint8_t Padding[4];
772 uint8_t Padding[4];
853 // PLL 4
872 uint16_t InitGfx; // In mV(Q2) , should be 0?
873 uint16_t InitSoc; // In mV(Q2)
874 uint16_t InitU; // In Mv(Q2) not applicable
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H A Dsmu13_driver_if_v13_0_0.h42 #define NUM_UCLK_DPM_LEVELS 4
52 #define FEATURE_DPM_FCLK_BIT 4
190 #define THROTTLER_TEMP_MEM_BIT 4
215 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4
844 // PLL 4
863 uint16_t InitGfx; // In mV(Q2) , should be 0?
864 uint16_t InitSoc; // In mV(Q2)
865 uint16_t InitU; // In Mv(Q2)
912 uint32_t Reserved[4];
919 uint16_t DcTol; // mV Q2
[all …]
H A Dsmu14_driver_if_v14_0.h50 #define FEATURE_DPM_FCLK_BIT 4
199 #define THROTTLER_TEMP_MEM_BIT 4
223 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4
589 MEM_VENDOR_ETRON, // 4
697 #define PP_OD_FEATURE_FAN_CURVE_BIT 4
757 uint16_t VddGfxVmax; // in mV
820 uint16_t VddGfxVmax; // in mV
944 // PLL 4
949 uint8_t InitUclkLevel; // =0,1,2,3,4,5 frequency from FreqTableUclk
964 uint16_t InitGfx; // In mV(Q2) , should be 0?
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8952.yaml26 minItems: 4
27 maxItems: 4
32 Array of 4 integer values defining DVS voltages in microvolts. All values
42 enum: [0, 1, 2, 3, 4, 5, 6, 7]
46 - 0: 32mV/us
47 - 1: 16mV/us
48 - 2: 8mV/us
49 - 3: 4mV/us
50 - 4: 2mV/us
51 - 5: 1mV/us
[all …]
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_req_lat_if.c40 } coef_probs[4][2][2][6];
42 u8 y_mode_prob[4][16];
43 u8 switch_interp_prob[4][16];
73 u8 partition_prob[16][4];
75 u8 inter_mode_probs[7][4];
76 u8 skip_probs[4];
78 u8 tx_p8x8[2][4];
79 u8 tx_p16x16[2][4];
80 u8 tx_p32x32[2][4];
94 } eob_branch[4][2][2];
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/linux/include/dt-bindings/usb/
H A Dpd.h26 #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
29 #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) argument
32 #define PDO_FIXED(mv, ma, flags) \ argument
34 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
36 #define VSAFE5V 5000 /* mv units */
38 #define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
39 #define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
42 #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) argument
43 #define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) argument
50 #define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c53 /* Idx NT mV d T mV d db */
58 { .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } }, /* 4: 600 750 2 */
126 /* Idx NT mV d T mV df db */
131 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, /* 4: 600 600 0 */
362 /* Idx NT mV diff db */
367 { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */
381 /* Idx NT mV diff db */
384 { .bxt = { 48, 0, 0, 96, } }, /* 2: 200 4 */
386 { .bxt = { 32, 0, 0, 128, } }, /* 4: 250 0 */
388 { .bxt = { 54, 0, 0, 85, } }, /* 6: 250 4 */
[all …]
/linux/drivers/staging/media/rkvdec/
H A Drkvdec-vp9.c37 u8 coef_intra[4][2][128];
42 u8 y_mode[4][9];
47 u8 interp_filter[4][2];
49 u8 coef[2][4][2][128];
69 } mv; member
80 u8 is_inter[4];
103 u32 partition[16][4];
105 u32 inter[4][2];
106 u32 tx32p[2][4];
107 u32 tx16p[2][4];
[all …]
/linux/include/linux/usb/
H A Dpd.h19 PD_CTRL_REJECT = 4,
44 PD_DATA_SINK_CAP = 4,
59 PD_EXT_GET_BATT_STATUS = 4,
232 #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
235 #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) argument
238 #define PDO_FIXED(mv, ma, flags) \ argument
240 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
242 #define VSAFE5V 5000 /* mv units */
244 #define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
245 #define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
[all …]
/linux/drivers/scsi/
H A Dch.c77 static int vendor_firsts[CH_TYPES-4];
78 static int vendor_counts[CH_TYPES-4];
82 static const char * vendor_labels[CH_TYPES-4] = {
314 cmd[4] = 255; in ch_readconfig()
346 VPRINTK(KERN_INFO, "type #4 (dt): 0x%x+%d [data transfer]\n", in ch_readconfig()
354 for (i = 0; i < 4; i++) { in ch_readconfig()
440 cmd[4] = (elem >> 8) & 0xff; in ch_position()
459 cmd[4] = (src >> 8) & 0xff; in ch_move()
482 cmd[4] = (src >> 8) & 0xff; in ch_exchange()
562 (int)data[4],(int)data[5]); in ch_gstatus()
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/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l33.txt22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23 a value of 1 and will increase at a step size of 100mV until a maximum of
24 8000mV.
55 depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
62 stage enters LDO operation. Starts as a default value of 50mV for a value
63 of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
81 by 100mV per step to a maximum of 5500mV.
91 1800mV with a step size of 50mV up to a maximum value of 1750mV.
92 Default is 1800mV.
[all …]
/linux/Documentation/hwmon/
H A Dxdpe12284.rst41 - VR12.0 mode, 5-mV DAC - 0x01.
42 - VR12.5 mode, 10-mV DAC - 0x02.
43 - IMVP9 mode, 5-mV DAC - 0x03.
44 - AMD mode 6.25mV - 0x10.
52 indexes 1, 2 are for "iin" and 3, 4 for "iout":
54 **curr[3-4]_crit**
56 **curr[3-4]_crit_alarm**
58 **curr[1-4]_input**
60 **curr[1-4]_label**
62 **curr[1-4]_max**
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/linux/include/linux/mfd/
H A Dmenelaus.h21 extern int menelaus_set_vmem(unsigned int mV);
22 extern int menelaus_set_vio(unsigned int mV);
23 extern int menelaus_set_vmmc(unsigned int mV);
24 extern int menelaus_set_vaux(unsigned int mV);
25 extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
33 #define EN_VIO_SLEEP (1 << 4)
/linux/drivers/media/platform/verisilicon/
H A Dhantro_g2_vp9_dec.c24 MAX_REF_FRAMES = 4
57 * for ( i = 0; i < 4; i ++ ) { in start_prepare_run()
74 * probs in a special way. All probs which need updating, except MV-related, in start_prepare_run()
78 * inv_map_table[]), or zero to indicate no update. All MV-related probs which need in start_prepare_run()
206 .y_base = G2_REF_LUMA_ADDR(4), in config_ref_registers()
207 .c_base = G2_REF_CHROMA_ADDR(4), in config_ref_registers()
638 struct hantro_g2_mv_probs *mv; in config_probs() local
715 mv = &adaptive->mv; in config_probs()
717 memcpy(mv->joint, probs->mv.joint, sizeof(mv->joint)); in config_probs()
718 memcpy(mv->sign, probs->mv.sign, sizeof(mv->sign)); in config_probs()
[all …]
/linux/drivers/media/v4l2-core/
H A Dv4l2-vp9.c131 /* 8x8 -> 4x4 */
182 { /* tx = 4x4 */
217 { /* Coeff Band 4 */
262 { 4, 88, 151 },
267 { /* Coeff Band 4 */
315 { 4, 72, 135 },
319 { /* Coeff Band 4 */
323 { 4, 58, 122 },
369 { /* Coeff Band 4 */
423 { /* Coeff Band 4 */
[all …]
/linux/drivers/mfd/
H A Dmenelaus.c104 #define MENELAUS_LOWBAT_IRQ 4 /* Low battery */
135 #define MCT_CTRL2_S1CD_BUFEN (1 << 4)
448 static int menelaus_set_voltage(const struct menelaus_vtg *vtg, int mV, in menelaus_set_voltage() argument
463 "to %d mV (reg 0x%02x, val 0x%02x)\n", in menelaus_set_voltage()
464 vtg->name, mV, vtg->vtg_reg, val); in menelaus_set_voltage()
504 { 1100, 4 },
535 dev_dbg(&c->dev, "Setting VCORE FLOOR to %d mV and ROOF to %d mV\n", in menelaus_set_vcore_hw()
573 int menelaus_set_vmem(unsigned int mV) in menelaus_set_vmem() argument
577 if (mV == 0) in menelaus_set_vmem()
580 val = menelaus_get_vtg_value(mV, vmem_values, ARRAY_SIZE(vmem_values)); in menelaus_set_vmem()
[all …]
/linux/arch/riscv/purgatory/
H A Dentry.S18 mv s0, a0 /* The hartid of the current hart */
19 mv s1, a1 /* Phys address of the FDT image */
24 mv a0, s0
25 mv a1, s1
30 .align 4
/linux/Documentation/devicetree/bindings/input/
H A Dti,drv260x.yaml58 enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
67 vib-rated-mv:
71 If this is not set then the value will be defaulted to 3200 mV.
74 vib-overdrive-mv:
78 If this is not set then the value will be defaulted to 3200 mV.
106 vib-rated-mv = <3200>;
107 vib-overdrive-mv = <3200>;
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-stm32-usbphyc.yaml110 - <1> increases the level by 5 to 7 mV
111 - <2> increases the level by 10 to 14 mV
112 - <3> decreases the level by 5 to 7 mV
133 - <4> = 20.05 mA target current / nominal + 6.24%
155 - <2> = reduce the impedance by 4 ohms
166 - <1> = threshold shift by +7 mV
167 - <2> = threshold shift by -5 mV
168 - <3> = threshold shift by +14 mV
182 - <1> = offset of +5 mV
183 - <2> = offset of +10 mV
[all …]

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