4c0 (full) in projects: linux - OpenGrok search results

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Searched +full:4 +full:c0 (Results 1 – 25 of 465) sorted by relevance

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/linux/arch/arm/include/asm/hardware/
H A D	cp14.h	`45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0) 46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0) 47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0) 48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0) 49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0) 50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0) 51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0) 52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0) 53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2) 54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2) [all …]`
/linux/arch/arm/mm/
H A D	proc-v6.S	`43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 66 mcr p15, 0, r1, c7, c5, 4 @ ISB 80 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 81 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 110 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 111 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 113 mrc p15, 0, r2, c13, c0, 1 @ read current context ID [all …]`
H A D	proc-sa1100.S	`43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 56 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 59 mcr p15, 0, r0, c1, c0, 0 @ disable caches 77 mcr p15, 0, ip, c7, c10, 4 @ drain WB 81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 102 mov r0, r0 @ 4 nop padding 105 mov r0, r0 @ 4 nop padding 150 str lr, [sp, #-4]! 152 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB [all …]`
H A D	proc-xsc3.S	`57 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 91 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 94 mcr p15, 0, r0, c1, c0, 0 @ disable caches 112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 140 mcr p14, 0, r0, c7, c0, 0 @ go to idle 177 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier 178 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 207 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier [all …]`
H A D	proc-v7.S	`35 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 38 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mrc p15, 0, r2, c1, c0, 0 @ ctrl register 61 mcr p15, 0, r2, c1, c0, 0 @ disable MMU 134 .equ cpu_v7_suspend_size, 4 * 9 138 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 139 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 142 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 146 mrc p15, 0, r7, c2, c0, 1 @ TTB 1 148 mrc p15, 0, r11, c2, c0, 2 @ TTB control register [all …]`
H A D	proc-arm740.S	`48 mrc p15, 0, r0, c1, c0, 0 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 82 mov r0, #0x0000003F @ base = 0, size = 4GB 83 mcr p15, 0, r0, c6, c0 @ set area 0, default 86 ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) 87 mov r4, #10 @ 11 is the minimum (4KB) [all …]`
H A D	proc-mohawk.S	`43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 66 mcr p15, 0, ip, c7, c10, 4 @ drain WB 68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 84 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 151 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 190 mcr p15, 0, r0, c7, c10, 4 @ drain WB 212 mcr p15, 0, r0, c7, c10, 4 @ drain WB [all …]`
H A D	proc-arm940.S	`17 /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */ 19 #define CACHE_DSEGMENTS 4 41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mcr p15, 0, ip, c7, c10, 4 @ drain WB 59 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 117 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments 122 subs r1, r1, #1 << 4 [all …]`
H A D	proc-arm926.S	`52 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 55 mcr p15, 0, r0, c1, c0, 0 @ disable caches 73 mcr p15, 0, ip, c7, c10, 4 @ drain WB 77 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 93 mrc p15, 0, r1, c1, c0, 0 @ Read control register 94 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 101 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable [all …]`
H A D	proc-xscale.S	`70 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 72 sub pc, pc, #4 @ flush instruction pipeline 76 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 117 mrc p15, 0, r1, c1, c0, 1 119 mcr p15, 0, r1, c1, c0, 1 127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches 152 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 155 sub pc, pc, #4 @ flush pipeline 157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register [all …]`
H A D	cache-v7.S	44 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR 46 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR 57 add r2, r2, #4 @ SetShift 69 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR 101 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr 107 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register 109 movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p? 110 movt r1, #:upper16:(0x410fc090 >> 4) 111 teq r1, r2, lsr #4 @ test for errata affected core and if so... 129 mrc p15, 1, r0, c0, c0, 1 @ read clidr [all …]
H A D	proc-arm946.S	`25 #define CACHE_DSEGMENTS 4 /* fixed / 27 #define CACHE_DLIMIT (CACHE_DSIZE 4) /* benchmark needed */ 48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 65 mcr p15, 0, ip, c7, c10, 4 @ drain WB 66 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 69 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 79 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 111 mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments 112 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries [all …]`
H A D	proc-arm920.S	`60 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 63 mcr p15, 0, r0, c1, c0, 0 @ disable caches 81 mcr p15, 0, ip, c7, c10, 4 @ drain WB 85 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 88 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 98 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 168 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 205 mcr p15, 0, r0, c7, c10, 4 @ drain WB 227 mcr p15, 0, r0, c7, c10, 4 @ drain WB [all …]`
H A D	proc-fa526.S	`38 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 41 mcr p15, 0, r0, c1, c0, 0 @ disable caches 56 .align 4 62 mcr p15, 0, ip, c7, c10, 4 @ drain WB 66 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 70 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 80 .align 4 90 mcr p15, 0, r0, c7, c10, 4 @ drain WB 103 .align 4 114 mcr p15, 0, ip, c7, c10, 4 @ data write barrier [all …]`
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A D	g98.fuc0s	`77 .align 4 185 ld b32 $r7 D[$r5 + $r6 * 4] 241 add b32 $r5 ((#ctx_dma - 0x60 * 4) & 0xffff) 254 ld b32 $r5 D[$r4 + 4] 379 ld b32 $r4 D[$r0 + #swap + 4] 514 cxsin $c0 515 cxsout $c0 525 cxsin $c0 526 cenc $c0 $c0 527 cxsout $c0 [all …]`
/linux/tools/testing/selftests/cgroup/
H A D	test_cpuset_prs.sh	`13 exit 4 # ksft_skip 216 " C0-1 . . C2-3 S+ C4-5 . . 0 A2:0-1" 217 " C0-1 . . C2-3 P1 . . . 0 " 218 " C0-1 . . C2-3 P1:S+ C0-1:P1 . . 0 " 219 " C0-1 . . C2-3 P1:S+ C1:P1 . . 0 " 220 " C0-1:S+ . . C2-3 . . . P1 0 " 221 " C0-1:P1 . . C2-3 S+ C1 . . 0 " 222 " C0-1:P1 . . C2-3 S+ C1:P1 . . 0 " 223 " C0-1:P1 . . C2-3 S+ C1:P1 . P1 0 " 224 " C0-1:P1 . . C2-3 C4-5 . . . 0 A1:4-5" [all …]`
/linux/arch/arm/kernel/
H A D	hyp-stub.S	`116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR) 120 mcr p15, 4, r7, c1, c1, 0 @ HCR 121 mcr p15, 4, r7, c1, c1, 2 @ HCPTR 122 mcr p15, 4, r7, c1, c1, 3 @ HSTR 126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR 128 mrc p15, 4, r7, c1, c1, 1 @ HDCR 130 mcr p15, 4, r7, c1, c1, 1 @ HDCR 133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR 137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR 139 mrc p15, 0, r7, c0, c0, 0 @ MIDR [all …]`
/linux/drivers/gpu/drm/tidss/
H A D	tidss_scale_coefs.c	17 .c2 = { 28, 34, 40, 46, 52, 58, 64, 70, 0, 2, 4, 8, 12, 16, 20, 24, }, 19 .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, }, 23 .c2 = { 24, 28, 32, 38, 44, 50, 56, 64, 0, 2, 4, 6, 8, 12, 16, 20, }, 25 .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, }, 29 .c2 = { 16, 20, 24, 30, 36, 42, 48, 56, 0, 0, 0, 2, 4, 8, 12, 14, }, 31 .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, }, 35 .c2 = { 12, 14, 16, 22, 28, 34, 40, 48, 0, 0, 0, 2, 4, 4, 4, 8, }, 37 .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, }, 41 .c2 = { 0, 2, 4, 8, 12, 18, 24, 32, 0, 0, 0, -2, -4, -4, -4, -2, }, 43 .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, }, [all …]
/linux/lib/crypto/s390/
H A D	chacha-s390.S	`14 #define FRAME (16 * 8 + 4 * 8) 97 VLM XA0,XA3,0x60,%r7,4 # load [smashed] sigma 442 #define C0 %v2 macro 491 VLM K0,BEPERM,0,%r7,4 # load sigma, increments, ... 511 VAF D4,D2,T2 # K[3]+4 514 VLR C0,K2 545 VAF C0,C0,D0 551 VX B0,B0,C0 583 VAF C0,C0,D0 589 VX B0,B0,C0 [all …]`
/linux/arch/arm/boot/compressed/
H A D	head.S	`38 mcr p14, 0, \ch, c0, c5, 0 44 mcr p14, 0, \ch, c8, c0, 0 50 mcr p14, 0, \ch, c1, c0, 0 141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR 145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR 290 ldr r2, [r1, #4] @ get &_edata 333 ldr r6, [r0, #4] 383 ldr r5, [r6, #4] 435 ldr r5, [r6, #4] 583 str r1, [r11], #4 @ next entry [all …]`
/linux/lib/crypto/
H A D	polyval.c	51 * With 64-bit multiplicands and one term every 4 bits, there would be in clmul64() 52 * up to 64 / 4 = 16 one bits per column when each multiplication is in clmul64() 55 * fit in 4 bits. Carries would sometimes overflow into the next term. in clmul64() 58 * 5 x 5 = 25 multiplications instead of 4 x 4 = 16. in clmul64() 60 * Instead, mask off 4 bits from one multiplicand, giving a max of 15 in clmul64() 61 * one bits per column. Then handle those 4 bits separately. in clmul64() 74 u128 c0 = (a0 * (u128)b0) ^ (a1 * (u128)b3) ^ in clmul64() local 83 /* Multiply the low 4 bits of @a by @b. / in clmul64() 92 out_lo = (((u64)c0) & 0x1111111111111111) ^ in clmul64() 96 *out_hi = (((u64)(c0 >> 64)) & 0x1111111111111111) ^ in clmul64() [all …]
/linux/arch/arm/mach-sunxi/
H A D	headsmp.S	`25 mrc p15, 0, r1, c0, c0, 0 37 mrc p15, 1, r1, c15, c0, 4 39 mcr p15, 1, r1, c15, c0, 4 42 mrc p15, 1, r1, c15, c0, 0 47 mcr p15, 1, r1, c15, c0, 0 50 mrc p15, 1, r1, c9, c0, 2 53 mcr p15, 1, r1, c9, c0, 2`
/linux/arch/arm/mach-tegra/
H A D	sleep.S	`40 mrc p15, 0, r2, c1, c0, 0 43 mcrne p15, 0, r2, c1, c0, 0 65 mrc p15, 0, r0, c0, c0, 5 66 ubfx r0, r0, #8, #4 70 mrc p15, 0x1, r0, c9, c0, 2 75 mcrne p15, 0x1, r0, c9, c0, 2 116 mrc p15, 0, r3, c1, c0, 0 120 mcr p15, 0, r3, c1, c0, 0 146 orr r0, r0, #(4 << 4) @ use PLLP in run mode burst`
/linux/tools/testing/selftests/hid/tests/
H A D	test_multitouch.py	33 "ALWAYS_VALID": BIT(4), 339 Unit Exponent (-4) 401 Unit Exponent (-4) 471 Unit Exponent (-4) 496 …c0 c0 05 0d 09 06 15 00 26 ff 00 a1 01 85 02 75 08 95 3f 09 00 82 02 01 95 3f 09 00 92 02 01 c0 05… 1137 …c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 01 c0 c0 05 0d 09 0e a1 01 85 11 09 23 a1 02 09 52 09… 1148 …c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 03 c0 c0 05 0d 09 0e a1 01 85 11 09 23 a1 02 09 52 09… 1159 …4d 46 70 03 81 02 09 31 26 ff 2b 46 f1 01 81 02 46 00 00 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95… 1196 …c0 09 22 a1 02 05 0d 35 00 45 00 55 00 65 00 09 42 25 01 75 01 81 02 09 32 81 02 09 47 81 02 75 05… 1206 …4b 46 70 03 81 02 09 31 26 ff 2b 46 f1 01 81 02 46 00 00 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95… [all …]
/linux/arch/arm/mach-shmobile/
H A D	headsmp.S	`37 1: .space 4 48 mrc p15, 0, r0, c0, c0, 5 @ r0 = MPIDR 53 mrc p15, 0, r1, c1, c0, 0 @ r1 = SCTLR 74 .align 4 86 .space 4 97 mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR 142 .space NR_CPUS * 4 145 .space NR_CPUS * 4 148 .space NR_CPUS * 4`

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