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/linux/Documentation/fb/
H A Dviafb.modes13 # Resolution 640 480
22 # 80 chars 480 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
30 geometry 640 480 640 480 32
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
38 # Resolution 640 480
47 # 80 chars 480 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt35510.c9 * 480x864, 480x854, 480x800, 480x720 and 480x640 pixel displays.
10 * It has 480x840x24bit SRAM embedded for storing a frame.
11 * When powered on the display is by default in 480x800 mode.
201 * @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V
202 * in 0.1V steps the default is 0x05 which means 6.0V
230 * @avee: setting for AVEE ranging from 0x00 = -6.5V to 0x14 = -4.5V
231 * in 0.1V steps the default is 0x05 which means -6.0V
250 * @vcl: setting for VCL ranging from 0x00 = -2.5V to 0x11 = -4.0V
251 * in 1V steps, the default is 0x00 which means -2.5V
269 * @vgh: setting for VGH ranging from 0x00 = 7.0V to 0x0B = 18.0V
[all …]
H A Dpanel-widechips-ws2401.c3 * Panel driver for the WideChips WS2401 480x800 DPI RGB panel, used in
86 .hdisplay = 480,
87 .hsync_start = 480 + 8,
88 .hsync_end = 480 + 8 + 10,
89 .htotal = 480 + 8 + 10 + 8,
161 /* Configure resolution to 480RGBx800 */ in ws2401_power_on()
163 /* Set addressing mode Flip V(d0), Flip H(d1) RGB/BGR(d3) */ in ws2401_power_on()
168 mipi_dbi_command(dbi, WS2401_PSMPS, 0x06, 0x03, /* DDVDH: 4.6v */ in ws2401_power_on()
170 mipi_dbi_command(dbi, WS2401_NSMPS, 0x06, 0x03, /* DDVDH: -4.6v */ in ws2401_power_on()
174 0xb4, /* VGH:16.1v, VGL:-13.8v */ in ws2401_power_on()
[all …]
H A Dpanel-sitronix-st7701.c265 /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */ in st7701_init_sequence()
270 /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */ in st7701_init_sequence()
275 /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */ in st7701_init_sequence()
298 /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */ in st7701_init_sequence()
643 .hdisplay = 480,
644 .hsync_start = 480 + 38,
645 .hsync_end = 480 + 38 + 12,
646 .htotal = 480 + 38 + 12 + 12,
742 .hdisplay = 480,
743 .hsync_start = 480 + 40,
[all …]
H A Dpanel-ilitek-ili9322.c56 * VREG1 voltage regulator from 3.6V (0x00) to 6.0V (0x18) in 0.1V
57 * increments. 5.4V (0x12) is the default. This is the reference
209 * used (4.5V).
393 "can't write gamma V%d to 0x%02x (%d)\n", in ili9322_init()
610 .vdisplay = 480,
611 .vsync_start = 480 + 4,
612 .vsync_end = 480 + 4 + 1,
624 .vdisplay = 480,
625 .vsync_start = 480 + 4,
626 .vsync_end = 480 + 4 + 1,
[all …]
H A Dpanel-sitronix-st7703.c169 0x81, /* DSI_LDO_SEL = 1.7V, RTERM = 90 Ohm */ in xbd599_init_sequence()
208 /* NVDDD_SEL = -1.8V, VDDD_SEL = out of range (possibly 1.9V?) */ in xbd599_init_sequence()
254 0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */ in xbd599_init_sequence()
272 0x07, /* VREF_SEL = 4.2V */ in xbd599_init_sequence()
273 0x07 /* NVREF_SEL = 4.2V */); in xbd599_init_sequence()
276 0x2C, /* VCOMDC_F = -0.67V */ in xbd599_init_sequence()
277 0x2C /* VCOMDC_B = -0.67V */); in xbd599_init_sequence()
405 .vdisplay = 480,
406 .vsync_start = 480 + 18,
407 .vsync_end = 480 + 18 + 2,
[all …]
/linux/drivers/ata/
H A Dlibata-pata-timings.c35 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 50, 960, 0 },
36 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 30, 480, 0 },
39 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 20, 480, 0 },
57 #define ENOUGH(v, unit) (((v)-1)/(unit)+1) argument
58 #define EZ(v, unit) ((v)?ENOUGH(((v) * 1000), unit):0) argument
/linux/drivers/video/fbdev/
H A Dvalkyriefb.h102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
165 640, 480
[all …]
/linux/arch/arm/mach-omap2/
H A Dpdata-quirks.c56 * Configures GPIOs 126, 127 and 129 to 1.8V mode instead of 3.0V
146 u32 v; in am35xx_enable_emac_int() local
148 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_enable_emac_int()
149 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR | in am35xx_enable_emac_int()
151 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_enable_emac_int()
157 u32 v; in am35xx_disable_emac_int() local
159 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_disable_emac_int()
160 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR); in am35xx_disable_emac_int()
161 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_disable_emac_int()
172 u32 v; in am35xx_emac_reset() local
[all …]
/linux/drivers/video/fbdev/geode/
H A Dlxfb_core.c39 { NULL, 60, 640, 480, 39682, 48, 8, 25, 2, 88, 2,
47 { NULL, 70, 640, 480, 35014, 88, 24, 15, 2, 64, 3,
50 { NULL, 72, 640, 480, 32102, 120, 16, 20, 1, 40, 3,
54 { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3,
58 { NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3,
62 { NULL, 90, 640, 480, 26392, 96, 32, 22, 1, 64, 3,
65 { NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3,
68 { NULL, 60, 640, 480, 39682, 48, 16, 25, 10, 88, 2,
302 u32 v; in lxfb_setcolreg() local
307 v = chan_to_field(red, &info->var.red); in lxfb_setcolreg()
[all …]
H A Dgx1fb_core.c31 { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
34 { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
37 { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
168 u32 v; in gx1fb_setcolreg() local
173 v = chan_to_field(red, &info->var.red); in gx1fb_setcolreg()
174 v |= chan_to_field(green, &info->var.green); in gx1fb_setcolreg()
175 v |= chan_to_field(blue, &info->var.blue); in gx1fb_setcolreg()
177 pal[regno] = v; in gx1fb_setcolreg()
H A Dgxfb_core.c43 { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
46 { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
49 { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
191 u32 v; in gxfb_setcolreg() local
196 v = chan_to_field(red, &info->var.red); in gxfb_setcolreg()
197 v |= chan_to_field(green, &info->var.green); in gxfb_setcolreg()
198 v |= chan_to_field(blue, &info->var.blue); in gxfb_setcolreg()
200 pal[regno] = v; in gxfb_setcolreg()
/linux/drivers/video/fbdev/core/
H A Dmodedb.c21 #define name_matches(v, s, l) \ argument
22 ((v).name && !strncmp((s), (v).name, (l)) && strlen((v).name) == (l))
23 #define res_matches(v, x, y) \ argument
24 ((v).xres == (x) && (v).yres == (y))
43 { NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
59 { NULL, 72, 640, 480, 31746, 144, 40, 30, 8, 40, 3, 0,
63 { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0,
72 { NULL, 85, 640, 480, 27777, 80, 56, 25, 1, 56, 3, 0,
88 { NULL, 100, 640, 480, 21834, 96, 32, 36, 8, 96, 6, 0,
244 /* 480x300 @ 56 Hz, 35.2 kHz hsync, 8:5 aspect ratio */
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-goni.dts47 regulator-name = "V_TF_2.8V";
101 regulator-name = "VALIVE_1.1V";
108 regulator-name = "VUSB+MIPI_1.1V";
115 regulator-name = "VADC_3.3V";
121 regulator-name = "VTF_2.8V";
127 regulator-name = "VCC_3.3V";
133 regulator-name = "VLCD_1.8V";
140 regulator-name = "VUSB+VDAC_3.3V";
146 regulator-name = "VCC+VCAM_2.8V";
152 regulator-name = "VPLL_1.1V";
[all …]
/linux/Documentation/devicetree/bindings/riscv/
H A Dsunxi.yaml7 title: Allwinner RISC-V SoC-based boards
15 Allwinner RISC-V SoC-based boards
51 - sipeed,lichee-rv-86-panel-480p
/linux/Documentation/devicetree/bindings/display/panel/
H A Dsamsung,lms380kf01.yaml9 description: The LMS380KF01 is a 480x800 DPI display panel from Samsung Mobile
38 usually around 3.0 V
42 around 1.8 V
H A Dsamsung,s6d27a1.yaml9 description: The S6D27A1 is a 480x800 DPI display panel from Samsung Mobile
37 usually around 3.0 V
41 around 1.8 V
H A Dseiko,43wvf1g.yaml7 title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel
26 description: 5v analog regulator
/linux/drivers/media/usb/gspca/
H A Dov534.c92 {640, 480, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
94 .sizeimage = 640 * 480 * 2,
102 {640, 480, V4L2_PIX_FMT_SGRBG8, V4L2_FIELD_NONE,
104 .sizeimage = 640 * 480,
113 {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
115 .sizeimage = 640 * 480 * 3 / 8 + 590,
178 {0xc1, 0x3c}, /* VSize 480 */
184 {0x31, 0xf9}, /* enable 1.8V Suspend */
362 {0x50, 0x00}, /* H/V divider=0 */
364 {0x52, 0x3c}, /* input V=480/4 */
[all …]
H A Dw996Xcf.c43 {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
45 .sizeimage = 640 * 480 * 2,
189 static void w9968cf_smbus_write_byte(struct sd *sd, u8 v) in w9968cf_smbus_write_byte() argument
195 sda = (v & 0x80) ? 2 : 0; in w9968cf_smbus_write_byte()
196 v <<= 1; in w9968cf_smbus_write_byte()
206 static void w9968cf_smbus_read_byte(struct sd *sd, u8 *v) in w9968cf_smbus_read_byte() argument
212 *v = 0; in w9968cf_smbus_read_byte()
214 *v <<= 1; in w9968cf_smbus_read_byte()
217 *v |= (w9968cf_read_sb(sd) & 0x0008) ? 1 : 0; in w9968cf_smbus_read_byte()
355 unsigned long hw_bufsize = sd->sif ? (352 * 288 * 2) : (640 * 480 * 2), in w9968cf_init()
[all …]
/linux/drivers/video/fbdev/sis/
H A Dsis_main.h176 {"640x480x8", {0x2e,0x2e}, 0x0101, 0x0101, 640, 480, 8, 1, 80, 30, MD_SIS300|MD_SIS315},
177 {"640x480x16", {0x44,0x44}, 0x0111, 0x0111, 640, 480, 16, 1, 80, 30, MD_SIS300|MD_SIS315},
178 {"640x480x24", {0x62,0x62}, 0x013a, 0x0112, 640, 480, 32, 1, 80, 30, MD_SIS300|MD_SIS315},
179 {"640x480x32", {0x62,0x62}, 0x013a, 0x0112, 640, 480, 32, 1, 80, 30, MD_SIS300|MD_SIS315},
180 {"720x480x8", {0x31,0x31}, 0x0000, 0x0000, 720, 480, 8, 1, 90, 30, MD_SIS300|MD_SIS315},
181 {"720x480x16", {0x33,0x33}, 0x0000, 0x0000, 720, 480, 16, 1, 90, 30, MD_SIS300|MD_SIS315},
182 {"720x480x24", {0x35,0x35}, 0x0000, 0x0000, 720, 480, 32, 1, 90, 30, MD_SIS300|MD_SIS315},
183 /*30*/ {"720x480x32", {0x35,0x35}, 0x0000, 0x0000, 720, 480, 32, 1, 90, 30, MD_SIS300|MD_SIS31…
192 {"800x480x8", {0x70,0x70}, 0x0000, 0x0000, 800, 480, 8, 1, 100, 30, MD_SIS300|MD_SIS315},
193 /*40*/ {"800x480x16", {0x7a,0x7a}, 0x0000, 0x0000, 800, 480, 16, 1, 100, 30, MD_SIS300|MD_SIS31…
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-icore.dts3 * Copyright (C) 2016 Amarula Solutions B.V.
47 vactive = <480>;
/linux/drivers/iio/adc/
H A Dsc27xx_adc.c76 /* ADC specific channel reference voltage 3.5V */
79 /* ADC default channel reference voltage is 2.8V */
125 * through 2 points in the linear graph. If the voltage is less than 1.2v, we
126 * should use the small-scale graph, and if more than 1.2v, we should use the
241 return SC27XX_VOLT_RATIO(480, 1955); in sc2720_adc_get_ratio()
243 return SC27XX_VOLT_RATIO(480, 2586); in sc2720_adc_get_ratio()
342 return SC27XX_VOLT_RATIO(480, 1955); in sc2730_adc_get_ratio()
344 return SC27XX_VOLT_RATIO(480, 2586); in sc2730_adc_get_ratio()
499 * the default 2.8v to 3.5v. in sc27xx_adc_read()
506 dev_err(data->dev, "failed to set the volref 3.5v\n"); in sc27xx_adc_read()
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmt9v032.txt4 an active array size of 752H x 480V. It is programmable through a simple
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850-evm.dts68 timing0: timing-480x272 {
70 hactive = <480>;
345 regulator-name = "VDCDC1_3.3V";
353 regulator-name = "VDCDC2_3.3V";
362 regulator-name = "VDCDC3_1.2V";
371 regulator-name = "LDO1_1.8V";
379 regulator-name = "LDO2_1.2V";

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