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/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6-cpu-opp.dtsi11 opp-480000000 {
13 opp-hz = /bits/ 64 <480000000>;
H A Dsun50i-h616-cpu-opp.dtsi10 opp-480000000 {
11 opp-hz = /bits/ 64 <480000000>;
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a774b1-hihope-rzg2n.dts22 memory@480000000 {
H A Dr8a77961-ulcb.dts22 memory@480000000 {
H A Dr8a774b1-hihope-rzg2n-rev2.dts22 memory@480000000 {
H A Dr8a77961-salvator-xs.dts22 memory@480000000 {
H A Dr8a779m3-salvator-xs.dts26 memory@480000000 {
H A Dr8a779m3-ulcb.dts25 memory@480000000 {
H A Dr8a779f4-s4sk.dts41 memory@480000000 {
H A Dr8a779f0-spider-cpu.dtsi57 memory@480000000 {
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-peripherals-opp.dtsi993 opp-480000000-1100 {
995 opp-hz = /bits/ 64 <480000000>;
1004 opp-480000000-1100 {
1006 opp-hz = /bits/ 64 <480000000>;
1015 opp-480000000-1100 {
1017 opp-hz = /bits/ 64 <480000000>;
H A Dtegra30-peripherals-opp.dtsi1619 opp-480000000-1000 {
1621 opp-hz = /bits/ 64 <480000000>;
1630 opp-480000000-1000 {
1632 opp-hz = /bits/ 64 <480000000>;
1641 opp-480000000-1000 {
1643 opp-hz = /bits/ 64 <480000000>;
/linux/drivers/clk/mxs/
H A Dclk-imx28.c168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
H A Dclk-imx23.c113 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a33.dtsi77 opp-480000000 {
78 opp-hz = /bits/ 64 <480000000>;
H A Dsun8i-a83t.dtsi207 opp-480000000 {
208 opp-hz = /bits/ 64 <480000000>;
260 opp-480000000 {
261 opp-hz = /bits/ 64 <480000000>;
/linux/drivers/phy/
H A Dphy-lpc18xx-usb-otg.c33 ret = clk_set_rate(lpc->clk, 480000000); in lpc18xx_usb_otg_phy_init()
/linux/drivers/clk/tegra/
H A Dclk-tegra114.c457 { 12000000, 480000000, 960, 12, 2, 12 },
458 { 13000000, 480000000, 960, 13, 2, 12 },
459 { 16800000, 480000000, 400, 7, 2, 5 },
460 { 19200000, 480000000, 200, 4, 2, 3 },
461 { 26000000, 480000000, 960, 26, 2, 12 },
470 .vco_min = 480000000,
H A Dclk-tegra30.c278 { 12000000, 480000000, 960, 12, 2, 12 },
279 { 13000000, 480000000, 960, 13, 2, 12 },
280 { 16800000, 480000000, 400, 7, 2, 5 },
281 { 19200000, 480000000, 200, 4, 2, 3 },
282 { 26000000, 480000000, 960, 26, 2, 12 },
1228 { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
H A Dclk-tegra124.c720 { 12000000, 480000000, 960, 12, 2, 12 },
721 { 13000000, 480000000, 960, 13, 2, 12 },
722 { 16800000, 480000000, 400, 7, 2, 5 },
723 { 19200000, 480000000, 200, 4, 2, 3 },
724 { 26000000, 480000000, 960, 26, 2, 12 },
733 .vco_min = 480000000,
H A Dclk-tegra20.c215 { 12000000, 480000000, 960, 12, 1, 0 },
216 { 13000000, 480000000, 960, 13, 1, 0 },
217 { 19200000, 480000000, 200, 4, 1, 0 },
218 { 26000000, 480000000, 960, 26, 1, 0 },
/linux/drivers/clk/imx/
H A Dclk-pfdv2.c105 480000000, in clk_pfdv2_determine_rate()
/linux/drivers/clk/qcom/
H A Dcamcc-sa8775p.c579 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
600 F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
621 F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
643 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
678 F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
/linux/drivers/clk/at91/
H A Dclk-utmi.c20 #define UTMI_RATE 480000000
/linux/drivers/clk/
H A Dclk-en7523.c90 static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
93 static const u32 crypto_base[] = { 540000000, 480000000 };

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