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/freebsd/sys/x86/cpufreq/
H A Dest.c84 /* Convert MHz and mV into IDs for passing to the MSR. */
85 #define ID16(MHz, mV, bus_clk) \ argument
86 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
91 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ argument
92 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
93 #define FREQ_INFO(MHz, mV, bus_clk) \ argument
94 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
116 * Frequency (MHz) and voltage (mV) settings.
665 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
669 /* 2.00GHz Centaur C7-M 533 Mhz FSB */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron-mickey.dts86 * and don't let the GPU go faster than 400 MHz.
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
139 /* At very hot, don't let GPU go over 300 MHz */
180 /* After 1st level throttle the GPU down to as low as 400 MHz */
200 /* When hot, GPU goes down to 300 MHz */
206 /* When really hot, don't let GPU go _above_ 300 MHz */
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15_a7.dts44 capacity-dmips-mhz = <1024>;
54 capacity-dmips-mhz = <1024>;
64 capacity-dmips-mhz = <516>;
74 capacity-dmips-mhz = <516>;
84 capacity-dmips-mhz = <516>;
162 compatible = "arm,cci-400";
169 compatible = "arm,cci-400-ctrl-if";
175 compatible = "arm,cci-400-ctrl-if";
181 compatible = "arm,cci-400-pmu,r0";
245 /* Reference 24MHz clock */
/freebsd/sys/contrib/ncsw/Peripherals/FM/MAC/
H A Dfman_dtsec_mii_acc.c40 * @dtsec_freq: dtsec clock frequency (in Mhz)
44 * of 1.5 to 2.5Mhz
53 * dtsec freq MgmtClk div MII freq Mhz
59 * [281..400] 6 (1/20)(1/8) [1.1 to 2.5]
75 else if (dtsec_freq < 400) mgmt_clk = 6; in dtsec_mii_get_div()
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnuvoton,nau8325.yaml47 and FS are within the range. MCLK range is from 2.048MHz to 24.576MHz.
49 MCLK_SRC/LRCK of 256, 400 or 500, and needs to detect the BCLK
/freebsd/sys/contrib/device-tree/src/arm64/cix/
H A Dsky1.dtsi24 capacity-dmips-mhz = <403>;
32 capacity-dmips-mhz = <403>;
40 capacity-dmips-mhz = <403>;
48 capacity-dmips-mhz = <403>;
51 cpu4: cpu@400 {
56 capacity-dmips-mhz = <1024>;
64 capacity-dmips-mhz = <1024>;
72 capacity-dmips-mhz = <1024>;
80 capacity-dmips-mhz = <1024>;
88 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/imx/
H A Dnxp,imx8mq-dcss.yaml73 - description: Must be 800 MHz
74 - description: Must be 400 MHz
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Dspacemit,k1-i2c.yaml39 fast speed mode : up to 400000 (400Hz)
40 high speed mode : up to 3300000 (3.3Mhz)
/freebsd/sys/contrib/dev/athk/ath11k/
H A Ddebugfs_htt_stats.h467 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
473 * (400us, 800us, 1600us & 3200us) in each mcs (0-11)
505 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1263 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1269 * in each GI (400us, 800us, 1600us & 3200us) in each mcs (0-11)
1353 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1769 * ... where max_bw == 4 for 160mhz
1806 * continuously in backpressure state for 300 - 400ms.
1808 * continuously in backpressure state for 400 - 500ms.
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-r1.dts82 entry-latency-us = <400>;
102 capacity-dmips-mhz = <1024>;
119 capacity-dmips-mhz = <1024>;
136 capacity-dmips-mhz = <578>;
153 capacity-dmips-mhz = <578>;
170 capacity-dmips-mhz = <578>;
187 capacity-dmips-mhz = <578>;
H A Djuno-r2.dts82 entry-latency-us = <400>;
102 capacity-dmips-mhz = <1024>;
120 capacity-dmips-mhz = <1024>;
138 capacity-dmips-mhz = <485>;
156 capacity-dmips-mhz = <485>;
174 capacity-dmips-mhz = <485>;
192 capacity-dmips-mhz = <485>;
H A Djuno.dts81 entry-latency-us = <400>;
101 capacity-dmips-mhz = <1024>;
119 capacity-dmips-mhz = <1024>;
137 capacity-dmips-mhz = <578>;
155 capacity-dmips-mhz = <578>;
173 capacity-dmips-mhz = <578>;
191 capacity-dmips-mhz = <578>;
H A Dcorstone1000.dtsi43 compatible = "arm,gic-400";
72 /* Reference 24MHz clock x 2 */
88 /* UART clock - 50MHz */
/freebsd/share/man/man4/
H A Dral.477 It can achieve speeds up to 144Mbps (20MHz bandwidth) and 300Mbps (40MHz
164 .It "Fiberline WL-400P" Ta RT2560 Ta PCI
165 .It "Fibreline WL-400X" Ta RT2560 Ta CardBus
/freebsd/sys/net80211/
H A Dieee80211_regdomain.h145 CTRY_JORDAN = 400, /* Jordan */
258 SKU_SR9 = 0x0298, /* Ubiquiti SR9 (900MHz/GSM) */
259 SKU_XR9 = 0x0299, /* Ubiquiti XR9 (900MHz/GSM) */
260 SKU_GZ901 = 0x029a, /* Zcomax GZ-901 (900MHz/GSM) */
261 SKU_XC900M = 0x029b, /* Xagyl XC900M (900MHz/GSM) */
266 * offset channel spacing (905MHz-
267 * 925MHz) versus the XR9 (907MHz-
268 * 922MHz), giving an extra channel.
/freebsd/sys/dev/videomode/
H A Dmodelines22 ModeLine "640x400" 31.5 640 672 736 832 400 401 404 445 -hsync +vsync
25 ModeLine "720x400" 28.32 720 738 846 900 400 412 414 449 -hsync +vsync
28 ModeLine "720x400" 35.5 720 756 828 936 400 401 404 446 -hsync +vsync
31 ModeLine "720x400" 35.5 720 738 846 900 400 421 423 449 -hsync -vsync
117 # 1680x1050 @ 60.00Hz (GTF) hsync: 65.22 kHz; pclk: 147.14 MHz
/freebsd/sys/arm/allwinner/
H A Daw_thermal.c92 #define A83T_ADC_ACQUIRE_TIME 23 /* 24Mhz/(23 + 1) = 1us */
93 #define A83T_THERMAL_PER 1 /* 4096 * (1 + 1) / 24Mhz = 341 us */
100 #define A64_ADC_ACQUIRE_TIME 400 /* 4Mhz/(400 + 1) = 100 us */
101 #define A64_THERMAL_PER 24 /* 4096 * (24 + 1) / 4Mhz = 25.6 ms */
119 #define H5_ADC_ACQUIRE_TIME 479 /* 24Mhz/479 = 20us */
120 #define H5_THERMAL_PER 58 /* 4096 * (58 + 1) / 24Mhz = 10ms */
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dac14xx.dts26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
145 bus-frequency = <80000000>; /* 80 MHz ips bus */
/freebsd/sys/contrib/dev/iwlwifi/mvm/
H A Dlink.c441 int mhz = nl80211_chan_width_to_mhz(chan_width); in iwl_mvm_get_puncturing_factor() local
444 if (WARN_ONCE(mhz < 20 || mhz > 320, in iwl_mvm_get_puncturing_factor()
445 "Invalid channel width : (%d)\n", mhz)) in iwl_mvm_get_puncturing_factor()
449 if (mhz < 80) in iwl_mvm_get_puncturing_factor()
453 n_subchannels = mhz / 20; in iwl_mvm_get_puncturing_factor()
629 .low = IWL_MVM_LOW_RSSI_THRESH_##_bw##MHZ, \
630 .high = IWL_MVM_HIGH_RSSI_THRESH_##_bw##MHZ \
642 /* 320 MHz has the same thresholds as 20 MHz */ in iwl_mvm_get_esr_rssi_thresh()
652 /* 6 GHz will always use 20 MHz thresholds, regardless of the BW */ in iwl_mvm_get_esr_rssi_thresh()
880 #define IWL_MVM_PREVENT_ESR_TIMEOUT (HZ * 400)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos2200.dtsi96 capacity-dmips-mhz = <260>;
106 capacity-dmips-mhz = <260>;
116 capacity-dmips-mhz = <260>;
126 capacity-dmips-mhz = <260>;
132 cpu4: cpu@400 {
136 capacity-dmips-mhz = <380>;
146 capacity-dmips-mhz = <380>;
156 capacity-dmips-mhz = <380>;
166 capacity-dmips-mhz = <488>;
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmtk-sd.txt38 - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
/freebsd/sys/sys/
H A Dcpu.h85 int freq; /* CPU clock in Mhz or 100ths of a percent. */
117 * frequency settings of 100, 200 and 300, 400 and a relative driver that
119 * levels of 50, 100, 150, 200, 300, 400.
/freebsd/sys/contrib/dev/athk/
H A Ddfs_pattern_detector.c61 ETSI_PATTERN(5, 0, 2, 300, 400, 3, 10, false),
62 ETSI_PATTERN(6, 0, 2, 400, 1200, 3, 15, false),
154 * @freq: frequency for this channel detector in MHz
229 * @freq: freq frequency in MHz
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3660.dtsi65 capacity-dmips-mhz = <592>;
79 capacity-dmips-mhz = <592>;
92 capacity-dmips-mhz = <592>;
105 capacity-dmips-mhz = <592>;
118 capacity-dmips-mhz = <1024>;
132 capacity-dmips-mhz = <1024>;
145 capacity-dmips-mhz = <1024>;
158 capacity-dmips-mhz = <1024>;
171 entry-latency-us = <400>;
189 entry-latency-us = <400>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf201.dts113 /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
168 /* TF201 Unknown 1GB LPDDR2 500MHZ */
225 /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
405 /* TF201 Unknown 1GB LPDDR2 500MHZ */

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