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Searched +full:400 +full:khz (Results 1 – 25 of 152) sorted by relevance

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/linux/drivers/i2c/
H A Di2c-core-acpi.c347 * These Silead touchscreen controllers only work at 400KHz, for
348 * some reason they do not work at 100KHz. On some devices the ACPI
350 * of 100KHz, testing has shown that these other devices work fine
351 * at 400KHz (as can be expected of any recent i2c hw) so we force
352 * the speed of the bus to 400 KHz if a Silead device is present.
360 * When a 400KHz freq is used on this model of ELAN touchpad in Linux,
363 * V15 G4) ACPI tables specify a 400KHz frequency for this device and
364 * some I2C busses (e.g, Designware I2C) default to a 400KHz freq,
365 * force the speed to 100KHz as a workaround.
371 * a 400KHz frequency. The root cause of the issue is not known.
/linux/Documentation/i2c/busses/
H A Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dxfer_mode_rate.h53 #define XFERRATE_I3C_SDR_FM_FMP 0x05 /* 400 KHz / 1 MHz */
57 #define XFERRATE_I2C_FM 0x00 /* 400 KHz */
/linux/Documentation/dev-tools/
H A Dgpio-sloppy-logic-analyzer.rst67 snippet which analyzes an I2C bus at 400kHz on a Renesas Salvator-XS board, the
70 parameter. The bus speed is 400kHz. So, the sampling theorem says we need to
71 sample at least at 800kHz. However, falling edges of both signals in an I2C
/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
H A Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
[all …]
H A Dnuvoton,nau8325.yaml48 FS range is from 8kHz to 96kHz. And also needs to detect the ratio
49 MCLK_SRC/LRCK of 256, 400 or 500, and needs to detect the BCLK
/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-reference-design-tablet.dtsi88 * The gsl1680 is rated at 400KHz and it will not work reliable at
89 * 100KHz, this has been confirmed on multiple different q8 tablets.
90 * All other devices on this bus are also rated for 400KHz.
/linux/Documentation/hwmon/
H A Dmcp3021.rst36 compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rt6245-regulator.yaml63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
/linux/drivers/i2c/busses/
H A Di2c-stm32.h19 STM32_I2C_SPEED_STANDARD, /* 100 kHz */
20 STM32_I2C_SPEED_FAST, /* 400 kHz */
H A Di2c-designware-common.c205 * Only standard mode at 100kHz, fast mode at 400kHz, in i2c_dw_validate_speed()
214 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n", in i2c_dw_validate_speed()
531 * transfer supported by the driver (for 400KHz this is in __i2c_dw_disable()
560 * transfer supported by the driver (for 400kHz this is in __i2c_dw_disable()
H A Di2c-ismt.c147 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
148 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
149 #define ISMT_SPGT_SPD_400K (0x2U << 30) /* 400 kHz */
198 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
756 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); in ismt_hw_init()
762 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); in ismt_hw_init()
767 case 400: in ismt_hw_init()
768 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); in ismt_hw_init()
774 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); in ismt_hw_init()
780 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); in ismt_hw_init()
[all …]
/linux/Documentation/devicetree/bindings/iio/pressure/
H A Dhoneywell,hsc030pa.yaml31 exceed 800kHz and the MOSI signal is not required.
65 400MD, 600MD, 001BD, 1.6BD, 2.5BD, 004BD, 2.5MG, 004MG, 006MG,
66 010MG, 016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG,
68 250KA, 400KA, 600KA, 001GA, 160LD, 250LD, 400LD, 600LD, 001KD,
70 100KD, 160KD, 250KD, 400KD, 250LG, 400LG, 600LG, 001KG, 1.6KG,
72 160KG, 250KG, 400KG, 600KG, 001GG, 015PA, 030PA, 060PA, 100PA,
/linux/Documentation/devicetree/bindings/tpm/
H A Dtcg,tpm-tis-i2c.yaml42 - infineon,slb9635tt # TPM 1.2 (maximum 100 kHz)
43 - infineon,slb9645tt # TPM 1.2 (maximum 400 kHz)
/linux/sound/firewire/fireface/
H A Dff-protocol-latter.c62 // 0x00: 32.0 kHz
63 // 0x01: 44.1 kHz
64 // 0x02: 48.0 kHz
65 // 0x04: 64.0 kHz
66 // 0x05: 88.2 kHz
67 // 0x06: 96.0 kHz
68 // 0x08: 128.0 kHz
69 // 0x09: 176.4 kHz
70 // 0x0a: 192.0 kHz
269 // IEEE 1394a (400 Mbps), Analog 1-12 and AES are available in latter_begin_session()
[all …]
/linux/include/linux/
H A Dwm97xx.h53 #define WM97XX_CM_RATE_8K 0x00f0 /* 8kHz continuous rate */
54 #define WM97XX_CM_RATE_12K 0x01f0 /* 12kHz continuous rate */
55 #define WM97XX_CM_RATE_24K 0x02f0 /* 24kHz continuous rate */
56 #define WM97XX_CM_RATE_48K 0x03f0 /* 48kHz continuous rate */
74 #define WM9712_PIL 0x0100 /* current used for pressure measurement. set 400uA else 200uA */
91 #define WM9705_PIL 0x0080 /* current used for pressure measurement. set 400uA else 200uA */
H A Dclocksource.h55 * @freq_khz: Clocksource frequency in khz.
68 * 400-499: Perfect
173 * clocksource_khz2mult - calculates mult from khz and shift
174 * @khz: Clocksource frequency in KHz
177 * Helper functions that converts a khz counter frequency to a timsource
180 static inline u32 clocksource_khz2mult(u32 khz, u32 shift_constant) in clocksource_khz2mult() argument
182 return clocksource_freq2mult(khz, shift_constant, NSEC_PER_MSEC); in clocksource_khz2mult()
235 * clocksource_register_hz/khz
256 static inline int clocksource_register_khz(struct clocksource *cs, u32 khz) in clocksource_register_khz() argument
258 return __clocksource_register_scale(cs, 1000, khz); in clocksource_register_khz()
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Dopencores,i2c-ocores.yaml45 frequency is fixed at 100 KHz.
109 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
/linux/sound/soc/codecs/
H A Dmax9877.c32 0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
51 "1176KHz",
52 "1100KHz",
53 "700KHz",
H A Dmax98363.c327 "Reserved", "0", "+FS/2", "-FS/2", "1KHz",
328 "12KHz", "8KHz", "6KHz", "4KHz", "3KHz",
329 "2KHz", "1.5KHz", "Reserved", "500Hz", "250Hz"
339 "400ms", "480ms", "560ms", "640ms",
/linux/drivers/media/radio/
H A Dlm7000.h29 freq /= 400; /* Convert to 25 kHz units */ in lm7000_set_freq()
/linux/Documentation/devicetree/bindings/input/
H A Diqs269a.yaml183 3: 2 MHz (500 kHz)
248 default: 400
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
392 3: 500 kHz (125 kHz)
580 azoteq,timeout-tap-ms = <400>;
/linux/Documentation/driver-api/
H A Di2c.rst10 I2C devices use seven bit addresses, and bus speeds of up to 400 kHz;
/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30-ringneck-haikou-lvds-9904379.dtso67 /* EEPROM and GT928 are limited to 400KHz */

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