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/freebsd/sys/dev/videomode/
H A Dmodelines18 # 640x350 @ 85Hz (VESA) hsync: 37.9kHz
21 # 640x400 @ 85Hz (VESA) hsync: 37.9kHz
22 ModeLine "640x400" 31.5 640 672 736 832 400 401 404 445 -hsync +vsync
24 # 720x400 @ 70Hz (EDID established timing) hsync: 31.47kHz
25 ModeLine "720x400" 28.32 720 738 846 900 400 412 414 449 -hsync +vsync
27 # 720x400 @ 85Hz (VESA) hsync: 37.9kHz
28 ModeLine "720x400" 35.5 720 756 828 936 400 401 404 446 -hsync +vsync
30 # 720x400 @ 88Hz (EDID established timing) hsync: 39.44kHz
31 ModeLine "720x400" 35.5 720 738 846 900 400 421 423 449 -hsync -vsync
33 # 640x480 @ 60Hz (Industry standard) hsync: 31.5kHz
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
H A Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all...]
H A Dnuvoton,nau8325.yaml48 FS range is from 8kHz to 96kHz. And also needs to detect the ratio
49 MCLK_SRC/LRCK of 256, 400 or 500, and needs to detect the BCLK
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun5i-reference-design-tablet.dtsi88 * The gsl1680 is rated at 400KHz and it will not work reliable at
89 * 100KHz, this has been confirmed on multiple different q8 tablets.
90 * All other devices on this bus are also rated for 400KHz.
H A Dsun8i-reference-design-tablet.dtsi67 * The gsl1680 is rated at 400KHz and it will not work reliable at
68 * 100KHz, this has been confirmed on multiple different q8 tablets.
H A Dsun6i-a31.dtsi110 /* kHz uV */
125 /* kHz uV */
140 /* kHz uV */
155 /* kHz uV */
1058 compatible = "arm,gic-400";
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rt6245-regulator.yaml63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-ocores.txt25 Defaults to 100 KHz when the property is not specified
37 frequency is fixed at 100 KHz.
69 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
H A Dopencores,i2c-ocores.yaml45 frequency is fixed at 100 KHz.
109 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
H A Di2c-lpc2k.txt13 absence of this property the default value is used (100 kHz).
16 i2c0: i2c@400a1000 {
/freebsd/sys/contrib/device-tree/Bindings/tpm/
H A Dtcg,tpm-tis-i2c.yaml42 - infineon,slb9635tt # TPM 1.2 (maximum 100 kHz)
43 - infineon,slb9645tt # TPM 1.2 (maximum 400 kHz)
/freebsd/sys/contrib/device-tree/Bindings/iio/pressure/
H A Dhoneywell,hsc030pa.yaml31 exceed 800kHz and the MOSI signal is not required.
65 400MD, 600MD, 001BD, 1.6BD, 2.5BD, 004BD, 2.5MG, 004MG, 006MG,
66 010MG, 016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG,
68 250KA, 400KA, 600KA, 001GA, 160LD, 250LD, 400LD, 600LD, 001KD,
70 100KD, 160KD, 250KD, 400KD, 250LG, 400LG, 600LG, 001KG, 1.6KG,
72 160KG, 250KG, 400KG, 600KG, 001GG, 015PA, 030PA, 060PA, 100PA,
/freebsd/share/man/man4/
H A Deventtimers.460 When enabled, called with frequency about 8KHz.
73 kern.eventtimer.choice: HPET(550) LAPIC(400) i8254(100) RTC(0)
76 kern.eventtimer.et.LAPIC.quality: 400
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
286 3: 500 kHz (125 kHz)
400 3: 2 MHz (500 kHz)
604 1: 2 MHz (500 kHz)
605 2: 1 MHz (250 kHz)
606 3: 500 kHz (125 kHz)
800 azoteq,timeout-tap-ms = <400>;
/freebsd/sys/contrib/device-tree/src/arm/synaptics/
H A Dberlin2q.dtsi35 /* kHz uV */
53 /* kHz uV */
71 /* kHz uV */
89 /* kHz uV */
245 gpio0: gpio@400 {
H A Dberlin2.dtsi40 /* kHz uV */
57 /* kHz uV */
184 gpio0: gpio@400 {
H A Dberlin2cd.dtsi38 /* kHz uV */
174 gpio0: gpio@400 {
/freebsd/sys/arm/ti/
H A Dti_i2c.c110 * The prescaler values for 100KHz and 400KHz modes come from the table in the
560 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps. in ti_i2c_reset()
570 * 400K bps or 3.4M bps (for the second phase of HS mode). These in ti_i2c_reset()
/freebsd/sys/dev/ismt/
H A Dismt.c113 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
114 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
115 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
/freebsd/sys/arm/allwinner/
H A Daw_rtc.c95 #define IS_LEAP_YEAR(y) (((y) % 400) == 0 || (((y) % 100) != 0 && ((y) % 4) == 0))
119 .iosc_freq = 650000, /* between 600 and 700 Khz */
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-tiger.dtsi221 * but SOC can handle only up to (400kHz).
445 regulator-enable-ramp-delay = <400>;
/freebsd/sys/arm/freescale/imx/
H A Dimx_i2c.c635 * and the actual i2c bus speeds that leads to, for nominal 100KHz and in i2c_reset()
636 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. in i2c_reset()
/freebsd/sys/dev/sdhci/
H A Dsdhci.h68 /* Alternate clock source is required when supplying a 400 KHz clock. */
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap5.dtsi53 /* kHz uV */
72 /* kHz uV */
742 prm_dsp: prm@400 {

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