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/linux/arch/xtensa/include/asm/
H A Dtlbflush.h6 * Copyright (C) 2001 - 2013 Tensilica Inc.
17 #define ITLB_ARF_WAYS 4
18 #define DTLB_ARF_WAYS 4
21 #define DTLB_HIT_BIT 4
27 * - flush_tlb_all() flushes all processes TLB entries
28 * - flush_tlb_mm(mm) flushes the specified mm context TLB entries
29 * - flush_tlb_page(vma, page) flushes a single page
30 * - flush_tlb_range(vma, vmaddr, end) flushes a range of pages
130 static inline void write_dtlb_entry (pte_t entry, int way) in write_dtlb_entry() argument
133 : : "r" (way), "r" (entry) ); in write_dtlb_entry()
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
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H A Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
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/linux/arch/arc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
175 * Flush the entire MM for userland. The fastest way is to move to Next ASID
185 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
189 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
190 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
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/linux/arch/mips/mm/
H A Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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H A Dc-r4k.c22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
29 #include <asm/cpu-features.h>
30 #include <asm/cpu-type.h>
38 #include <asm/mips-cps.h>
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
46 * R4K_INDEX - Index based cache operations.
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ in r4k_op_needs_ipi()
74 * be needed, but only if there are foreign CPUs (non-siblings with in r4k_op_needs_ipi()
388 * is not cached in the S-cache, we know it also won't be in local_r4k___flush_cache_all()
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/linux/arch/powerpc/mm/nohash/
H A Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
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/linux/arch/powerpc/platforms/powernv/
H A Dsubcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
37 * ------------|------------------
39 * 2-way split | 2
40 * 4-way split | 4
46 * ----------------------------
48 * ----------------------------
49 * Thread | 0 1 2 3 4 5 6 7 |
50 * ----------------------------
52 * 2-way split:
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/linux/arch/arm64/boot/dts/broadcom/
H A Dbcm2712.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
18 clock-frequency = <54000000>;
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/linux/arch/x86/crypto/
H A Dblowfish-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 .file "blowfish-x86_64-asm.S"
15 #define s0 ((16 + 2) * 4)
16 #define s1 ((16 + 2 + (1 * 256)) * 4)
17 #define s2 ((16 + 2 + (2 * 256)) * 4)
18 #define s3 ((16 + 2 + (3 * 256)) * 4)
57 * 1-way blowfish
64 movl s0(CTX,RT0,4), RT0d; \
65 addl s1(CTX,RT1,4), RT0d; \
69 xorl s2(CTX,RT1,4), RT0d; \
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/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
31 #define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)
45 #define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
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/linux/arch/mips/kernel/
H A Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
74 #define CP0_BRCM_MODE_ClkRATIO_MASK (7 << 4)
85 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG0 4 << 3
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
137 /* sets per way = (64<<IS) */
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
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/linux/arch/arm/mm/
H A Dcache-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7.S
16 #include <asm/hardware/cache-b15-rac.h>
18 #include "proc-macros.S"
20 .arch armv7-a
52 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
54 moveq r1, #1 @ r1 needs value > 0 even if only 1 way
57 add r2, r2, #4 @ SetShift
65 subs r0, r0, #1 @ Set--
67 subs r3, r3, r1 @ Way--
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H A Dcache-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7m.S
5 * Based on linux/arch/arm/mm/cache-v7.S
20 #include "proc-macros.S"
22 .arch armv7-m
51 * dcisw: Invalidate data cache by set/way
58 * dccisw: Clean and invalidate data cache by set/way
132 and r3, r1, r0, lsr #3 @ NumWays - 1
136 add r0, r0, #4 @ SetShift
140 1: sub r2, r2, #1 @ NumSets--
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H A Dproc-arm940.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
13 #include <asm/pgtable-hwdef.h>
15 #include "proc-macros.S"
17 /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
19 #define CACHE_DSEGMENTS 4
42 bic r0, r0, #0x00001000 @ i-cache
43 bic r0, r0, #0x00000004 @ d-cache
58 mcr p15, 0, ip, c7, c10, 4 @ drain WB
61 bic ip, ip, #0x00001000 @ i-cache
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H A Dproc-feroceon.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
5 * Heavily based on proc-arm926.S
15 #include <asm/pgtable-hwdef.h>
18 #include "proc-macros.S"
51 tst r0, #(1 << 16) @ get way
53 movne r3, #((4 - 1) << 30) @ 4-way
55 moveq r3, #0 @ 1-way
75 mcr p15, 0, r0, c7, c10, 4 @ drain WB
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB
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/linux/arch/sh/mm/
H A Dcache-sh2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh2.c
23 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_wback_region()
25 & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
28 int way; in sh2__flush_wback_region() local
29 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
30 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
33 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
44 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
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/linux/Documentation/admin-guide/
H A Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
9 4 = /dev/port I/O port access
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
61 4 = /dev/fd?d360 5.25" 360K in a 360K drive(1)
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
74 CVMX_L2C_EVENT_DATA_HIT = 4,
133 CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4,
183 * Return the L2 Cache way partitioning for a given core.
189 * -1 on error
199 * a way, while a 1 bit blocks the core from evicting any
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/linux/arch/sparc/mm/
H A Dleon_mm.c1 // SPDX-License-Identifier: GPL-2.0
32 return (retval & SRMMU_CTX_PMASK) << 4; in leon_get_ctable_ptr()
65 printk(KERN_INFO "swprobe: --- ctx (%x) ---\n", ctx); in leon_swprobe()
67 pgd = LEON_BYPASS_LOAD_PA(ctxtbl + (ctx * 4)); in leon_swprobe()
83 printk(KERN_INFO "swprobe: --- pgd (%x) ---\n", pgd); in leon_swprobe()
85 ptr = (pgd & SRMMU_PTD_PMASK) << 4; in leon_swprobe()
86 ptr += ((((vaddr) >> LEON_PGD_SH) & LEON_PGD_M) * 4); in leon_swprobe()
105 printk(KERN_INFO "swprobe: --- pmd (%x) ---\n", pmd); in leon_swprobe()
107 ptr = (pmd & SRMMU_PTD_PMASK) << 4; in leon_swprobe()
108 ptr += (((vaddr >> LEON_PMD_SH) & LEON_PMD_M) * 4); in leon_swprobe()
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/linux/fs/xfs/libxfs/
H A Dxfs_errortag.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2000-2002,2005 Silicon Graphics, Inc.
11 * There are two ways to use this header file. The first way is to #include it
13 * with the XFS_TEST_ERROR macro. The second way is to enclose the #include
27 #define XFS_ERRTAG_IFLUSH_4 4
53 * Drop-writes support removed because write error handling cannot trash
54 * pre-existing delalloc extents in any useful way anymore. We retain the
100 XFS_ERRTAG(BTREE_CHECK_LBLOCK, btree_chk_lblk, XFS_RANDOM_DEFAULT/4) \
119 XFS_ERRTAG(AG_RESV_CRITICAL, ag_resv_critical, 4) \
136 XFS_ERRTAG(METAFILE_RESV_CRITICAL, metafile_resv_crit, 4)
/linux/tools/testing/selftests/net/forwarding/
H A DREADME9 (dev->netns_immutable) and most of them probably do not support the
10 L1-separation provided by namespaces.
17 vrf-h1 | vrf-h2
18 + +---+---
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/linux/Documentation/devicetree/bindings/mux/
H A Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
20 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
21 0-7 for an 8-way multiplexer, etc.
25 --------------------
28 specifier using the '#mux-control-cells' or '#mux-state-cells' property.
29 The value of '#mux-state-cells' will always be one greater than the value
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/linux/Documentation/networking/
H A Dnexthop-group-resilient.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Resilient Next-hop Groups
7 Resilient groups are a type of next-hop group that is aimed at minimizing
12 the legacy multipath next-hop group, which uses the hash-threshold
15 To select a next hop, hash-threshold algorithm first assigns a range of
22 +-------+-------+-------+-------+-------+
23 | 1 | 2 | 3 | 4 | 5 |
24 +-------+-+-----+---+---+-----+-+-------+
25 | 1 | 2 | 4 | 5 |
26 +---------+---------+---------+---------+
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/linux/arch/powerpc/platforms/cell/
H A Dspu_callbacks.c1 // SPDX-License-Identifier: GPL-2.0-only
22 * 1. They interact with the way SPU syscalls are handled
27 * 3. They are somewhat interacting with the system in a way
30 * 4. They are optional and we can't rely on them being
47 if (s->nr_ret >= ARRAY_SIZE(spu_syscall_table)) { in spu_sys_callback()
48 pr_debug("%s: invalid syscall #%lld", __func__, s->nr_ret); in spu_sys_callback()
49 return -ENOSYS; in spu_sys_callback()
52 syscall = spu_syscall_table[s->nr_ret]; in spu_sys_callback()
54 pr_debug("SPU-syscall " in spu_sys_callback()
57 s->nr_ret, in spu_sys_callback()
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