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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ring.c40 * Most engines on the GPU are fed via ring buffers. Ring
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
53 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission.
55 * @type: ring type for which to return the limit.
73 * amdgpu_ring_alloc - allocate space on the ring buffer
75 * @ring: amdgpu_ring structure holding ring information
76 * @ndw: number of dwords to allocate in the ring buffer
78 * Allocate @ndw dwords in the ring buffer (all asics).
81 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) in amdgpu_ring_alloc() argument
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H A Dsdma_v4_4_2.c111 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring);
112 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring);
121 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); in sdma_v4_4_2_get_reg_offset()
136 return -EINVAL; in sdma_v4_4_2_seq_to_irq_id()
148 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
153 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
158 return -EINVAL; in sdma_v4_4_2_irq_id_to_seq()
168 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
170 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); in sdma_v4_4_2_inst_init_golden_registers()
177 4); in sdma_v4_4_2_inst_init_golden_registers()
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H A Damdgpu_vpe.c34 /* VPE CSA resides in the 4th page of CSA */
40 #define VPE_MAX_DPM_LEVEL 4
85 remainder -= arg2_value; in vpe_u1_8_from_fraction()
87 } while (--i != 0); in vpe_u1_8_from_fraction()
114 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest),
123 struct amdgpu_device *adev = vpe->ring.adev; in amdgpu_vpe_configure_dpm()
126 if (adev->pm.dpm_enabled) { in amdgpu_vpe_configure_dpm()
135 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); in amdgpu_vpe_configure_dpm()
137 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); in amdgpu_vpe_configure_dpm()
141 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__); in amdgpu_vpe_configure_dpm()
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H A Damdgpu_sdma.c40 struct amdgpu_sdma_instance *amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring) in amdgpu_sdma_get_instance_from_ring() argument
42 struct amdgpu_device *adev = ring->adev; in amdgpu_sdma_get_instance_from_ring()
45 for (i = 0; i < adev->sdma.num_instances; i++) in amdgpu_sdma_get_instance_from_ring()
46 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_instance_from_ring()
47 ring == &adev->sdma.instance[i].page) in amdgpu_sdma_get_instance_from_ring()
48 return &adev->sdma.instance[i]; in amdgpu_sdma_get_instance_from_ring()
53 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index) in amdgpu_sdma_get_index_from_ring() argument
55 struct amdgpu_device *adev = ring->adev; in amdgpu_sdma_get_index_from_ring()
58 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_get_index_from_ring()
59 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_index_from_ring()
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H A Dvce_v4_0.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
56 * vce_v4_0_ring_get_rptr - get read pointer
58 * @ring: amdgpu_ring pointer
62 static uint64_t vce_v4_0_ring_get_rptr(struct amdgpu_ring *ring) in vce_v4_0_ring_get_rptr() argument
64 struct amdgpu_device *adev = ring->adev; in vce_v4_0_ring_get_rptr()
66 if (ring->me == 0) in vce_v4_0_ring_get_rptr()
68 else if (ring->me == 1) in vce_v4_0_ring_get_rptr()
75 * vce_v4_0_ring_get_wptr - get write pointer
77 * @ring: amdgpu_ring pointer
81 static uint64_t vce_v4_0_ring_get_wptr(struct amdgpu_ring *ring) in vce_v4_0_ring_get_wptr() argument
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H A Dgfx_v9_4_3.c178 struct amdgpu_device *adev = kiq_ring->adev; in gfx_v9_4_3_kiq_set_resources()
182 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_4_3_kiq_set_resources()
200 struct amdgpu_ring *ring) in gfx_v9_4_3_kiq_map_queues() argument
202 struct amdgpu_device *adev = kiq_ring->adev; in gfx_v9_4_3_kiq_map_queues()
203 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); in gfx_v9_4_3_kiq_map_queues()
204 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_4_3_kiq_map_queues()
205 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx_v9_4_3_kiq_map_queues()
212 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | in gfx_v9_4_3_kiq_map_queues()
213 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | in gfx_v9_4_3_kiq_map_queues()
214 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | in gfx_v9_4_3_kiq_map_queues()
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/linux/drivers/gpu/drm/radeon/
H A Dr600_dma.c34 * to the 3D engine (ring buffer, IBs, etc.), but the
43 * r600_dma_get_rptr - get the current read pointer
46 * @ring: radeon ring pointer
51 struct radeon_ring *ring) in r600_dma_get_rptr() argument
55 if (rdev->wb.enabled) in r600_dma_get_rptr()
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
64 * r600_dma_get_wptr - get the current write pointer
67 * @ring: radeon ring pointer
72 struct radeon_ring *ring) in r600_dma_get_wptr() argument
78 * r600_dma_set_wptr - commit the write pointer
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H A Dradeon_ring.c39 * Most engines on the GPU are fed via ring buffers. Ring
45 * pointers are equal, the ring is idle. When the host
46 * writes commands to the ring buffer, it increments the
50 static void radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
53 * radeon_ring_supports_scratch_reg - check if the ring supports
57 * @ring: radeon_ring structure holding ring information
59 * Check if a specific ring supports writing to scratch registers (all asics).
60 * Returns true if the ring supports writing to scratch regs, false if not.
63 struct radeon_ring *ring) in radeon_ring_supports_scratch_reg() argument
65 switch (ring->idx) { in radeon_ring_supports_scratch_reg()
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H A Dni.c52 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
55 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
63 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
66 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
439 switch (rdev->family) { in ni_init_golden_registers()
449 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
450 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
451 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
452 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
453 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
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H A Dcik_sdma.c38 * sDMA - System DMA
42 * and each one supports 1 ring buffer used for gfx
46 * (ring buffer, IBs, etc.), but sDMA has it's own
55 * cik_sdma_get_rptr - get the current read pointer
58 * @ring: radeon ring pointer
63 struct radeon_ring *ring) in cik_sdma_get_rptr() argument
67 if (rdev->wb.enabled) { in cik_sdma_get_rptr()
68 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_sdma_get_rptr()
70 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_rptr()
82 * cik_sdma_get_wptr - get the current write pointer
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H A Devergreen_dma.c31 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
36 * Add a DMA fence packet to the ring to write
38 * an interrupt if needed (evergreen-SI).
43 struct radeon_ring *ring = &rdev->ring[fence->ring]; in evergreen_dma_fence_ring_emit() local
44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
46 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); in evergreen_dma_fence_ring_emit()
47 radeon_ring_write(ring, addr & 0xfffffffc); in evergreen_dma_fence_ring_emit()
48 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
49 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
51 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); in evergreen_dma_fence_ring_emit()
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H A Dvce_v1_0.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
47 uint32_t nonce[4];
48 uint32_t sigval[4];
53 * vce_v1_0_get_rptr - get read pointer
56 * @ring: radeon_ring pointer
61 struct radeon_ring *ring) in vce_v1_0_get_rptr() argument
63 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) in vce_v1_0_get_rptr()
70 * vce_v1_0_get_wptr - get write pointer
73 * @ring: radeon_ring pointer
78 struct radeon_ring *ring) in vce_v1_0_get_wptr() argument
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H A Dni_dma.c35 * to the 3D engine (ring buffer, IBs, etc.), but the
45 * cayman_dma_get_rptr - get the current read pointer
48 * @ring: radeon ring pointer
53 struct radeon_ring *ring) in cayman_dma_get_rptr() argument
57 if (rdev->wb.enabled) { in cayman_dma_get_rptr()
58 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_dma_get_rptr()
60 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cayman_dma_get_rptr()
72 * cayman_dma_get_wptr - get the current write pointer
75 * @ring: radeon ring pointer
80 struct radeon_ring *ring) in cayman_dma_get_wptr() argument
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/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_ring2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
12 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_init() argument
14 u32 *ring_cfg = ring->state; in xgene_enet_ring_init()
15 u64 addr = ring->dma; in xgene_enet_ring_init()
17 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) { in xgene_enet_ring_init()
18 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
27 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
30 ring_cfg[4] |= SET_VAL(X2_SELTHRSH, 1); in xgene_enet_ring_init()
34 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_set_type() argument
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/linux/drivers/soc/ti/
H A Dk3-ringacc.c1 // SPDX-License-Identifier: GPL-2.0
3 * TI K3 NAVSS Ring Accelerator subsystem driver
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/dma-mapping.h>
14 #include <linux/dma/ti-cppi5.h>
15 #include <linux/soc/ti/k3-ringacc.h>
28 * struct k3_ring_rt_regs - The RA realtime Control/Status Registers region
31 * @db: Ring Doorbell Register
33 * @occ: Ring Occupancy Register
34 * @indx: Ring Current Index Register
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/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-io.json13 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
14 "ScaleUnit": "4Bytes",
29 …"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) t…
30 "ScaleUnit": "4Bytes",
66 "Counter": "4",
145 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
152 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
205 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
212 …plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
253 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
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/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-io.json34 "Counter": "4",
114 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
121 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
174 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
181 …plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
222 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
229 "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
234 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
240 "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
289 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
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/linux/drivers/net/ethernet/freescale/
H A Dgianfar.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
67 #define DRV_NAME "gfar-enet"
87 #define DEFAULT_LFC_PTVVAL 4
92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
95 #define TX_RING_MOD_MASK(size) (size-1)
96 #define RX_RING_MOD_MASK(size) (size-1)
281 /* weighted round-robin scheduling (WRRS) */
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/linux/drivers/net/ethernet/hisilicon/hns3/
H A Dhns3_enet.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
70 ((max_frm_size) - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
87 #define HNS3_RXD_L3ID_S 4
112 #define HNS3_RXD_OL3ID_S 4
121 #define HNS3_RXD_PTYPE_S 4
122 #define HNS3_RXD_PTYPE_M GENMASK(11, 4)
126 #define HNS3_RXD_VLD_B 4
144 #define HNS3_TXD_L3CS_B 4
163 #define HNS3_TXD_TUNTYPE_S 4
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/linux/drivers/dma/
H A Dfsl_raid.h13 * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
44 #define FSL_RE_MAX_CHANS 4
67 #define FSL_RE_RING_SIZE_MASK (FSL_RE_RING_SIZE - 1)
69 #define FSL_RE_ADDR_BIT_SHIFT 4
70 #define FSL_RE_ADDR_BIT_MASK (BIT(FSL_RE_ADDR_BIT_SHIFT) - 1)
114 u8 rsvd1[4];
116 u8 rsvd2[4];
118 u8 rsvd3[4];
138 u8 rsvd1[4];
140 u8 rsvd2[4];
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/linux/drivers/net/ethernet/intel/igc/
H A Digc.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define IGC_MAX_RX_QUEUES 4
26 #define IGC_MAX_TX_QUEUES 4
37 #define IGC_N_SDP 4
41 #define IGC_MAX_TX_TSTAMP_REGS 4
139 struct igc_ring *ring; /* pointer to linked list of rings */ member
144 u8 itr; /* current ITR setting for ring */
155 void *desc; /* descriptor ring memory */
156 unsigned long flags; /* ring specific flags */
157 void __iomem *tail; /* pointer to ring tail register */
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/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_regs_cn9k_pf.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 /* ################# Offsets of RING, EPF, MAC ######################### */
34 #define CN93_MAC_OFFSET (0x1ULL << 4)
35 #define CN93_BIT_ARRAY_OFFSET (0x1ULL << 4)
36 #define CN93_EPVF_RING_OFFSET (0x1ULL << 4)
61 /* ##### RING IN (Into device from PCI: Tx Ring) REGISTERS #### */
72 #define CN93_SDP_R_IN_CONTROL(ring) \ argument
73 (CN93_SDP_R_IN_CONTROL_START + ((ring) * CN93_RING_OFFSET))
75 #define CN93_SDP_R_IN_ENABLE(ring) \ argument
76 (CN93_SDP_R_IN_ENABLE_START + ((ring) * CN93_RING_OFFSET))
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_txrx.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
34 * the value of the rate limit is non-zero
37 #define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */
41 * i40e_intrl_usec_to_reg - convert interrupt rate limit to register
97 (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, (pf)->hw.caps) ? \
111 * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab)
112 * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab)
140 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; in i40e_compute_pad()
154 * cache-line alignment. in i40e_skb_pad()
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/linux/drivers/crypto/caam/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
12 tristate "Freescale CAAM-Multicore platform driver backend"
19 and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
20 This module creates job ring devices, and configures h/w
36 tristate "Freescale CAAM Job Ring driver backend"
42 and Assurance Module (CAAM). This module adds a job ring operation
51 int "Job Ring size"
56 range 2-9 (ring size 4-512).
58 2 => 4
60 4 => 16
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/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-cache.json15 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an…
24 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
34 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
44 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
54 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
64 …- this includes code, data, prefetches and hints coming from L2. This has numerous filters availa…
209 "BriefDescription": "LRU Queue; Non-0 Aged Victim",
214 "PublicDescription": "How often we picked a victim that had a non-zero age",
219 "BriefDescription": "AD Ring In Use; Counterclockwise",
224 …ring is being used at this ring stop. This includes when packets are passing by and when packets …
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