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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PerfectShuffle.h1 //===-- AArch64PerfectShuffle.h - AdvSIMD Perfect Shuffle Table -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file, which was autogenerated by llvm-PerfectShuffle, contains data
12 //===----------------------------------------------------------------------===//
26 // This table is 6561*4 = 26244 bytes in size.
29 2080972802U, // <0,0,0,1>: Cost 2 ins <0,0,u,1>, lane 2
31 2085707777U, // <0,0,0,3>: Cost 2 ins <0,u,0,3>, lane 1
32 1476398390U, // <0,0,0,4>: Cost 2 vext1 <0,0,0,0>, RHS
33 2080440323U, // <0,0,0,5>: Cost 2 ins <0,0,0,u>, lane 3
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_interface.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
120 * Parallel loopback from the PMA receive lane data ports, to the
121 * transmit lane data ports
178 * Tx de-emphasis parameters
183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
196 * Transmit Amplitude control signal. Used to define the full-scale
198 * 000 - Not Supported
199 * 001 - 952mVdiff-pkpk
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H A Dal_hal_serdes_internal_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
44 * Per lane register fields
47 * RX and TX lane hard reset
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
57 * RX and TX lane hard reset control
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
66 /* RX lane power state control */
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H A Dal_hal_serdes_hssp_internal_regs.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * Per lane register fields
46 * RX and TX lane hard reset
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
56 * RX and TX lane hard reset control
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
65 /* RX lane power state control */
74 /* TX lane power state control */
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H A Dal_hal_serdes_25g.c9 found at http://www.gnu.org/licenses/gpl-2.0.html
73 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base; in al_serdes_25g_reg_read()
94 return -1; in al_serdes_25g_reg_read()
97 al_reg_write32(&regs_base->gen.reg_addr, addr); in al_serdes_25g_reg_read()
98 *data = al_reg_read32(&regs_base->gen.reg_data); in al_serdes_25g_reg_read()
112 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base; in al_serdes_25g_reg_write()
132 return -1; in al_serdes_25g_reg_write()
135 al_reg_write32(&regs_base->gen.reg_addr, addr); in al_serdes_25g_reg_write()
136 al_reg_write32(&regs_base->gen.reg_data, (data | SERDES_C_GEN_REG_DATA_STRB_MASK)); in al_serdes_25g_reg_write()
202 return -1; in al_serdes_25g_mailbox_send_cmd()
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H A Dal_hal_serdes_hssp.c9 found at http://www.gnu.org/licenses/gpl-2.0.html
56 /* c(-1) configurations */
111 * Lane Rx rate change software flow disable
115 enum al_serdes_lane lane);
124 * Lane Rx rate change software flow enable if all conditions met
128 enum al_serdes_lane lane);
508 enum al_serdes_lane lane) in al_serdes_lane_rx_rate_change_sw_flow_en() argument
510 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 201, 0xfc); in al_serdes_lane_rx_rate_change_sw_flow_en()
511 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 202, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
512 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 203, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c1 /*-
49 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
67 #define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4))
68 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4))
69 #define USB2_PORT_CAP_PORT_CAP(p, x) (((x) & 3) << ((p) * 4))
76 #define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4))
77 #define SS_PORT_MAP_PORT_MAP(p, x) (((x) & 7) << ((p) * 4))
83 #define ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
84 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(x) (1 << (17 + (x) * 4))
85 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
56 #define FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(x, i) (((x) >> (11 + ((i) - 1) * 6)) & 0x3F);
68 #define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4))
69 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4))
70 #define USB2_PORT_CAP_PORT_CAP(p, x) (((x) & 3) << ((p) * 4))
77 #define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4))
78 #define SS_PORT_MAP_PORT_MAP(p, x) (((x) & 7) << ((p) * 4))
104 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_DIV_DET_EN (1 << 4)
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/freebsd/sys/dev/drm2/
H A Ddrm_dp_helper.c39 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
43 int lane) in dp_get_lane_status() argument
45 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
46 int s = (lane & 1) * 4; in dp_get_lane_status()
56 int lane; in drm_dp_channel_eq_ok() local
62 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
63 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
74 int lane; in drm_dp_clock_recovery_ok() local
77 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
78 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific Operands.
16 //===----------------------------------------------------------------------===//
101 return ((uint64_t)Imm) < 4;
256 // Register list of one D register, with byte lane subscripting.
266 // ...with half-word lane subscripting.
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/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Duncore-other.json11 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
23 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
166 "ScaleUnit": "4Bytes",
182 "ScaleUnit": "4Bytes",
198 "ScaleUnit": "4Bytes",
214 "ScaleUnit": "4Bytes",
227 "ScaleUnit": "4Bytes",
240 "ScaleUnit": "4Bytes",
253 "ScaleUnit": "4Bytes",
266 "ScaleUnit": "4Bytes",
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/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
299 uint32_t reserved51[4];
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
621 * [0x84] SERDES 32-bit interface bit selection
625 * [0x88] SERDES 32-bit interface bit selection
661 struct al_eth_mac_stat_lane stat_lane[4]; /* [0xd00] */
686 #define ETH_10G_MAC_CMD_CFG_PROMIS_EN (1 << 4)
717 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_9_CLK 4
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H A Dal_hal_eth_kr.c1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
41 * @brief KR HAL driver for main functions (auto-neg, Link Training)
173 #define AL_ETH_KR_PMD_LP_COEF_UP_PLUS_SHIFT 4
182 #define AL_ETH_KR_PMD_LP_STATUS_REPORT_PLUS_SHIFT 4
190 #define AL_ETH_KR_PMD_LD_COEF_UP_PLUS_SHIFT 4
199 #define AL_ETH_KR_PMD_LD_STATUS_REPORT_PLUS_SHIFT 4
212 enum al_eth_an_lt_lane lane) in al_eth_an_lt_reg_read() argument
217 if (adapter->rev_id < AL_ETH_REV_ID_3) { in al_eth_an_lt_reg_read()
218 al_assert(lane == AL_ETH_AN__LT_LANE_0); in al_eth_an_lt_reg_read()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp1 //===- X86InterleavedAccess.cpp -------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 /// optimization generating X86-specific instructions/intrinsics for
14 //===----------------------------------------------------------------------===//
43 /// X86-specific instructions/intrinsics.
47 /// %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> poison, <0, 2, 4, 6>
50 /// Reference to the wide-load instruction of an interleaved access
57 /// Reference to the starting index of each user-shuffle.
71 /// sub vectors of type \p T. Returns the sub-vectors in \p DecomposedVectors.
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3588-usbdp-phy
21 "#phy-cells":
24 - PHY_TYPE_USB3
25 - PHY_TYPE_DP
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H A Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
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H A Dqcom,msm8996-qmp-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb
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H A Dphy-cadence-sierra.txt2 -----------------------
5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets: Must contain an entry for each in reset-names.
9 - reset-names: Must include "sierra_reset" and "sierra_apb".
13 - reg: register range for the PHY.
14 - #address-cells: Must be 1
15 - #size-cells: Must be 0
18 - clocks: Must contain an entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
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H A Dqcom,qmp-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,ipq6018-qmp-usb3-phy
20 - qcom,ipq8074-qmp-usb3-phy
21 - qcom,msm8996-qmp-usb3-phy
22 - qcom,msm8998-qmp-usb3-phy
23 - qcom,qcm2290-qmp-usb3-phy
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/freebsd/sys/dev/hwpmc/
H A Dhwpmc_ppc970.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
46 ((r & ~(0x1f << (7 * (1 - i) + 1))) | (x << (7 * (1 - i) + 1)))
47 /* MMCR1 has 6 PMC*SEL items (PMC3->PMC8), in sequence. */
49 ((r & ~(0x1f << (5 * (7 - i) + 2))) | (x << (5 * (7 - i) + 2)))
56 * Encoding 00 000 -- Add byte lane bit counters
57 * MMCR1[24:31] -- select bit matching PMC being an adder.
59 * PMCxSEL: 1x -- select from byte lane: 10 == lower lane (0/1), 11 == upper
60 * lane (2/3).
61 * PMCxSEL[2:4] -- bit in the byte lane selected.
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/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A Duncore-other.json10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
20 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
164 "ScaleUnit": "7.11E-06Bytes",
174 "ScaleUnit": "7.11E-06Bytes",
186 "ScaleUnit": "4Bytes",
198 "ScaleUnit": "4Bytes",
210 "ScaleUnit": "4Bytes",
222 "ScaleUnit": "4Bytes",
237 "ScaleUnit": "4Bytes",
252 "ScaleUnit": "4Bytes",
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/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A Duncore-other.json10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
20 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
164 "ScaleUnit": "7.11E-06Bytes",
174 "ScaleUnit": "7.11E-06Bytes",
186 "ScaleUnit": "4Bytes",
198 "ScaleUnit": "4Bytes",
210 "ScaleUnit": "4Bytes",
222 "ScaleUnit": "4Bytes",
237 "ScaleUnit": "4Bytes",
252 "ScaleUnit": "4Bytes",
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dthine,thp7312.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Elder <paul.elder@@ideasonboard.com>
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
23 - $ref: /schemas/media/video-interface-devices.yaml#
36 thine,boot-mode:
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
46 reset-gpios:
52 vddcore-supply:
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/freebsd/sys/arm64/rockchip/
H A Drk_typec_phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
84 #define TX_TXCC_MGNFS_MULT_000(lane) ((0x4050 | ((lane) << 9)) << 2) argument
85 #define XCVR_DIAG_BIDI_CTRL(lane) ((0x40e8 | ((lane) << 9)) << 2) argument
86 #define XCVR_DIAG_LANE_FCM_EN_MGN(lane) ((0x40f2 | ((lane) << 9)) << 2) argument
87 #define TX_PSC_A0(lane) ((0x4100 | ((lane) << 9)) << 2) argument
88 #define TX_PSC_A1(lane) ((0x4101 | ((lane) << 9)) << 2) argument
89 #define TX_PSC_A2(lane) ((0x4102 | ((lane) << 9)) << 2) argument
90 #define TX_PSC_A3(lane) ((0x4103 | ((lane) << 9)) << 2) argument
91 #define TX_RCVDET_EN_TMR(lane) ((0x4122 | ((lane) << 9)) << 2) argument
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/freebsd/sys/contrib/libsodium/src/libsodium/crypto_pwhash/argon2/
H A Dargon2-fill-block-avx2.c18 #include "argon2-core.h"
41 # include "blamka-round-avx2.h"
54 for (i = 0; i < 4; ++i) { in fill_block()
55 BLAKE2_ROUND_1(state[8 * i + 0], state[8 * i + 4], state[8 * i + 1], state[8 * i + 5], in fill_block()
59 for (i = 0; i < 4; ++i) { in fill_block()
60 BLAKE2_ROUND_2(state[ 0 + i], state[ 4 + i], state[ 8 + i], state[12 + i], in fill_block()
84 for (i = 0; i < 4; ++i) { in fill_block_with_xor()
85 BLAKE2_ROUND_1(state[8 * i + 0], state[8 * i + 4], state[8 * i + 1], state[8 * i + 5], in fill_block_with_xor()
89 for (i = 0; i < 4; ++i) { in fill_block_with_xor()
90 BLAKE2_ROUND_2(state[ 0 + i], state[ 4 + i], state[ 8 + i], state[12 + i], in fill_block_with_xor()
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