| /linux/arch/hexagon/lib/ |
| H A D | memset.S | 24 #if __HEXAGON_ARCH__ < 3
28 r7 = extractu(r0, #3 , #0)
29 p0 = cmp.eq(r2, #0) define
36 if p0 jumpr r31 /* count == 0, so return */
41 p0 = tstbit(r9, #0) define
58 p0 = tstbit(r9, #1) define
60 if !p0 jump 3f /* skip initial byte store */
68 3: /* skip initial byte store */
71 p0 = tstbit(r9, #2) define
73 if !p0 jump 4f /* skip initial half store */
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| H A D | divsi3.S | 10 p0 = cmp.gt(r0,#-1) define
15 p3 = xor(p0,p1)
18 p0 = cmp.gtu(r3,r2) define
26 r0 = mux(p0,#0,r0)
27 p0 = or(p0,p1) define
28 if (p0.new) jumpr:nt r31
35 p0 = cmp.gtu(r6,#4) define
39 if (!p0) r6 = #3
50 if (!p0.new) r0 = add(r0,r5)
51 if (!p0.new) r2 = sub(r2,r4)
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| H A D | memcpy.S | 90 * prolog = prolog >> 3;
115 * epilogdws = epilog >> 3;
148 #define ifbyte p0 /* if transfer has bytes in epilog/prolog */
149 #define ifhword p0 /* if transfer has shorts in epilog/prolog */
150 #define ifword p0 /* if transfer has words in epilog/prolog */
151 #define noprolog p0 /* no prolog, xfer starts at 32byte */
153 #define noepilog p0 /* no epilog, xfer ends on 32byte boundary */
155 #define kernel1 p0 /* kernel count == 1 */
187 p0 = cmp.gtu(len, #23); /* %1, <24 */ define
194 len8 = lsr(len, #3); /* %8 < 97 */
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| /linux/arch/hexagon/mm/ |
| H A D | copy_user_template.S | 19 p0 = cmp.gtu(bytes,#0) define
20 if (!p0.new) jump:nt .Ldone
26 p0 = bitsclr(r3,#7) define
27 if (!p0.new) jump:nt .Loop_not_aligned_8
32 loopcount = lsr(bytes,#3)
46 bytes -= asl(loopcount,#3)
52 p0 = bitsclr(r4,#7) define
53 if (p0.new) jump:nt .Lalign
56 p0 = bitsclr(r3,#3) define
57 if (!p0.new) jump:nt .Loop_not_aligned_4
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| /linux/arch/x86/include/asm/ |
| H A D | xor_avx.h | 21 BLOCK(32 * (i + 3), 3)
29 static void xor_avx_2(unsigned long bytes, unsigned long * __restrict p0, in xor_avx_2() argument
42 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_2()
44 "=m" (p0[i / sizeof(*p0)])); \ in xor_avx_2()
49 p0 = (unsigned long *)((uintptr_t)p0 + 512); in xor_avx_2()
56 static void xor_avx_3(unsigned long bytes, unsigned long * __restrict p0, in xor_avx_3() argument
72 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_3()
74 "=m" (p0[i / sizeof(*p0)])); \ in xor_avx_3()
79 p0 = (unsigned long *)((uintptr_t)p0 + 512); in xor_avx_3()
87 static void xor_avx_4(unsigned long bytes, unsigned long * __restrict p0, in xor_avx_4() argument
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| /linux/tools/testing/selftests/cgroup/ |
| H A D | test_cpuset_prs.sh | 23 CGROUP2=$(mount -t cgroup2 | head -1 | awk -e '{print $3}')
194 SETUP_A123_PARTITIONS="C1-3:P1:S+ C2-3:P1:S+ C3:P1"
198 " C0-1 . . C2-3 S+ C4-5 . . 0 A2:0-1"
199 " C0-1 . . C2-3 P1 . . . 0 "
200 " C0-1 . . C2-3 P1:S+ C0-1:P1 . . 0 "
201 " C0-1 . . C2-3 P1:S+ C1:P1 . . 0 "
202 " C0-1:S+ . . C2-3 . . . P1 0 "
203 " C0-1:P1 . . C2-3 S+ C1 . . 0 "
204 " C0-1:P1 . . C2-3 S+ C1:P1 . . 0 "
205 " C0-1:P1 . . C2-3 S+ C1:P1 . P1 0 "
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| /linux/arch/hexagon/include/asm/ |
| H A D | cmpxchg.h | 32 " memw_locked(%1,P0) = %2;\n" /* store into memory */ in __arch_xchg()
33 " if (!P0) jump 1b;\n" in __arch_xchg()
36 : "memory", "p0" in __arch_xchg()
63 " { P0 = cmp.eq(%0,%2);\n" \
64 " if (!P0.new) jump:nt 2f; }\n" \
65 " memw_locked(%1,p0) = %3;\n" \
66 " if (!P0) jump 1b;\n" \
70 : "memory", "p0" \
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| H A D | atomic.h | 21 " memw_locked(%0,p0) = %1;\n" in arch_atomic_set()
22 " if (!P0) jump 1b;\n" in arch_atomic_set()
25 : "memory", "p0", "r6" in arch_atomic_set()
73 " %1 = "#op "(%0,%3);\n" \
119 " %1 = add(%0, %3);" in ATOMIC_OPS()
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| /linux/Documentation/scheduler/ |
| H A D | sched-util-clamp.rst | 12 of tasks. It was introduced in v5.3 release. The CGroup support was merged in
199 +- p0 +- p3 +- p4
227 Bucket 3: [615:819]
279 p0->uclamp[UCLAMP_MIN] = 300
280 p0->uclamp[UCLAMP_MAX] = 900
285 then assuming both p0 and p1 are enqueued to the same rq, both UCLAMP_MIN
311 :ref:`Section 3 <uclamp-interfaces>` discusses the interfaces and will expand
337 3. Interfaces
382 * cpu.uclamp.min is a protection as described in :ref:`section 3-3 of cgroup
391 * cpu.uclamp.max is a limit as described in :ref:`section 3-2 of cgroup v2
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| /linux/tools/memory-model/Documentation/ |
| H A D | litmus-tests.txt | 70 3 {}
72 5 P0(int *x, int *y)
105 Line 3 is the initialization section. Because the default initialization
114 The name of the first process is "P0" and that of the second "P1".
123 names are significant. The fact that both P0() and P1() have a formal
125 same global variable, also named "x". So the "int *x, int *y" on P0()
128 by reference, hence "P0(int *x, int *y)", but *never* "P0(int x, int y)".
130 P0() has no local variables, but P1() has two of them named "r0" and "r1".
145 The P0() process does "WRITE_ONCE(*x, 1)" on line 7. Because "x" is a
146 pointer in P0()'s parameter list, this does an unordered store to global
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| H A D | explanation.txt | 11 3. A SIMPLE EXAMPLE
116 P0()
132 Here the P0() function represents the interrupt handler running on one
135 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
163 instance, P1 might run entirely before P0 begins, in which case r1 and
164 r2 will both be 0 at the end. Or P0 might run entirely before P1
168 routines run concurrently. One possibility is that P1 runs after P0's
197 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
203 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
207 P0 stores 1 to buf before storing 1 to flag, since it executes
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| /linux/arch/arm/probes/kprobes/ |
| H A D | test-arm.c | 28 "3: adr lr, 2f \n\t" \
38 TEST_ARG_MEM(15, 3f+1) \
44 "3: adr lr, 2f \n\t" \
59 TEST_RR( op s "ne r1, r",1, VAL1,", r",2, val, ", lsl #3") \ in kprobe_arm_test_cases()
60 TEST_RR( op s "cs r2, r",3, VAL1,", r",2, val, ", lsr #4") \ in kprobe_arm_test_cases()
61 TEST_RR( op s "cc r3, r",3, VAL1,", r",2, val, ", asr #5") \ in kprobe_arm_test_cases()
65 TEST_R( op s "vc r6, r",7, VAL1,", pc, lsl #3") \ in kprobe_arm_test_cases()
69 TEST_RRR( op s "hi r8, r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")\ in kprobe_arm_test_cases()
86 TEST_RR( op "eq r",1, VAL1,", r",2, val, ", lsl #3") \ in kprobe_arm_test_cases()
87 TEST_RR( op "cc r",3, VAL1,", r",2, val, ", lsr #4") \ in kprobe_arm_test_cases()
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| /linux/tools/perf/bench/ |
| H A D | numa.c | 167 struct params p0; variable
170 OPT_INTEGER('p', "nr_proc" , &p0.nr_proc, "number of processes"),
171 OPT_INTEGER('t', "nr_threads" , &p0.nr_threads, "number of threads per process"),
173 OPT_STRING('G', "mb_global" , &p0.mb_global_str, "MB", "global memory (MBs)"),
174 OPT_STRING('P', "mb_proc" , &p0.mb_proc_str, "MB", "process memory (MBs)"),
175 …OPT_STRING('L', "mb_proc_locked", &p0.mb_proc_locked_str,"MB", "process serialized/locked memory a…
176 OPT_STRING('T', "mb_thread" , &p0.mb_thread_str, "MB", "thread memory (MBs)"),
178 OPT_UINTEGER('l', "nr_loops" , &p0.nr_loops, "max number of loops to run (default: unlimited)"),
179 OPT_UINTEGER('s', "nr_secs" , &p0.nr_secs, "max number of seconds to run (default: 5 secs)"),
180 OPT_UINTEGER('u', "usleep" , &p0.sleep_usecs, "usecs to sleep per loop iteration"),
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| /linux/drivers/scsi/qla4xxx/ |
| H A D | ql4_dbg.c | 17 printk(" 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh " in qla4xxx_dump_buffer()
106 offsetof(struct isp_reg, u2.isp4022.p0.ext_hw_conf), in qla4xxx_dump_registers()
107 readw(&ha->reg->u2.isp4022.p0.ext_hw_conf)); in qla4xxx_dump_registers()
109 offsetof(struct isp_reg, u2.isp4022.p0.port_ctrl), in qla4xxx_dump_registers()
110 readw(&ha->reg->u2.isp4022.p0.port_ctrl)); in qla4xxx_dump_registers()
112 offsetof(struct isp_reg, u2.isp4022.p0.port_status), in qla4xxx_dump_registers()
113 readw(&ha->reg->u2.isp4022.p0.port_status)); in qla4xxx_dump_registers()
115 (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_out), in qla4xxx_dump_registers()
116 readw(&ha->reg->u2.isp4022.p0.gp_out)); in qla4xxx_dump_registers()
118 (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in), in qla4xxx_dump_registers()
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| /linux/arch/arm/kernel/ |
| H A D | xscale-cp0.c | 22 "mrrc p0, 0, %0, %1, c0\n" in dsp_save_state()
29 "mcrr p0, 0, %0, %1, c0\n" in dsp_load_state()
126 * mar acc0, %2, %3 in cpu_has_iwmmxt()
130 * tmcrr wR0, %2, %3 in cpu_has_iwmmxt()
134 "mcrr p0, 0, %2, %3, c0\n" in cpu_has_iwmmxt()
135 "mrrc p0, 0, %0, %1, c0\n" in cpu_has_iwmmxt()
159 cp_access = xscale_cp_access_read() & ~3; in xscale_cp0_init()
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| /linux/drivers/media/pci/cx23885/ |
| H A D | cx23885-f300.c | 9 * GPIO0 - data - P0.3 F300
10 * GPIO1 - reset - P0.2 F300
11 * GPIO2 - clk - P0.1 F300
12 * GPIO3 - busy - P0.0 F300
147 buf[3] = 0x01;/* power on */ in f300_set_voltage()
152 buf[3] = 0x01; in f300_set_voltage()
157 buf[3] = 0x00;/* power off */ in f300_set_voltage()
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| /linux/drivers/soc/hisilicon/ |
| H A D | kunpeng_hccs.h | 10 * | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 |P0 | P1 | P2 | P3 |
139 #define HCCS_PORT_CONFIG 3
143 u8 link_fsm : 3; /* link fsm, 1: reset 2: setup 3: config 4: link-up */
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| /linux/drivers/parisc/ |
| H A D | eisa_enumerator.c | 46 return (x[3] << 24) | (x[2] << 16) | (x[1] << 8) | x[0]; in get_32()
64 vendor[3] = '\0'; in print_eisa_id()
194 len+=3; in configure_port()
205 * and at byte 3 the value to write starts.
224 get_8(buf+len+3)) | in configure_port_init()
228 outb(get_8(buf+len+3), get_16(buf+len+1)); in configure_port_init()
237 get_16(buf+len+3)) | in configure_port_init()
241 outw(cpu_to_le16(get_16(buf+len+3)), get_16(buf+len+1)); in configure_port_init()
249 get_32(buf+len+3)) | in configure_port_init()
252 outl(cpu_to_le32(get_32(buf+len+3)), get_16(buf+len+1)); in configure_port_init()
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| /linux/Documentation/arch/x86/ |
| H A D | resctrl.rst | 218 3 Non-temporal writes to non-local NUMA domain
234 0=0x7f;1=0x7f;2=0x7f;3=0x7f
237 0=0x15;1=0x15;3=0x15;4=0x15
247 0=0x33;1=0x7f;2=0x7f;3=0x7f
257 0=0x30;1=0x30;3=0x15;4=0x15
400 3) Otherwise the schemata for the default group is used.
411 3) Otherwise RDT events for the task will be reported in the root level
419 a task in a monitor group showing 3 MB of cache occupancy. If you move
421 groups you will likely see that the old group is still showing 3 MB and
644 L3DATA:0=fffff;1=fffff;2=fffff;3=fffff
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| /linux/tools/testing/selftests/arm64/fp/ |
| H A D | fp-ptrace-asm.S | 2 // Copyright (C) 2021-3 ARM Limited.
88 ldr z3, [x7, #3, MUL VL]
121 ldr p0, [x7]
124 wrffr p0.b
128 ldr p0, [x7, #0, MUL VL]
131 ldr p3, [x7, #3, MUL VL]
215 str z3, [x7, #3, MUL VL]
246 str p0, [x7, #0, MUL VL]
249 str p3, [x7, #3, MUL VL]
266 rdffr p0.b
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| H A D | sve-test.S | 102 lsr x\nrtmp, x\nrtmp, #3
158 // Beware: corrupts P0.
172 lsr x1, x1, #3
180 wrffr p0.b
265 // Beware -- corrupts P0.
273 lsr x5, x5, #3
279 rdffr p0.b
306 movi v31.8b, #3
308 // And P0
309 rdffr p0.b
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| /linux/arch/arm64/boot/dts/xilinx/ |
| H A D | zynqmp-zc1751-xm017-dc3.dts | 150 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
151 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
152 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
153 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
159 phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
193 phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
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| /linux/drivers/media/usb/pwc/ |
| H A D | pwc-dec23.c | 3 Decompression for chipset version 2 et 3
93 unsigned char *p0, *p8; in build_table_color() local
98 p0 = p0004[compression_mode]; in build_table_color()
102 for (j = 0; j < 8; j++, r++, p0 += 128) { in build_table_color()
107 else if (k >= 1 && k < 3) in build_table_color()
109 else if (k >= 3 && k < 6) in build_table_color()
116 bit = (r[0] >> 3) & 7; in build_table_color()
126 p0[k + 0x00] = (1 * pw) + 0x80; in build_table_color()
127 p0[k + 0x10] = (2 * pw) + 0x80; in build_table_color()
128 p0[k + 0x20] = (3 * pw) + 0x80; in build_table_color()
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| /linux/drivers/gpio/ |
| H A D | gpio-lpc32xx.c | 84 "p0.0", "p0.1", "p0.2", "p0.3",
85 "p0.4", "p0.5", "p0.6", "p0.7"
89 "p1.0", "p1.1", "p1.2", "p1.3",
98 "p2.0", "p2.1", "p2.2", "p2.3",
518 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; in lpc32xx_gpio_probe()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/ |
| H A D | dml_top_mcache.c | 167 const char MAX_SCL_VP_OVERLAP = 3; in calculate_h_split_for_scaling_transform()
289 params->mcache_allocations[plane_index].shift_granularity.p0, &p0shift); in dml2_top_mcache_validate_admissability()
324 per_plane_pipe_mcache_regs->main.p0.mcache_id_first = MCACHE_ID_UNASSIGNED; in reset_mcache_allocations()
325 per_plane_pipe_mcache_regs->main.p0.mcache_id_second = MCACHE_ID_UNASSIGNED; in reset_mcache_allocations()
326 per_plane_pipe_mcache_regs->main.p0.split_location = SPLIT_LOCATION_UNDEFINED; in reset_mcache_allocations()
328 per_plane_pipe_mcache_regs->mall.p0.mcache_id_first = MCACHE_ID_UNASSIGNED; in reset_mcache_allocations()
329 per_plane_pipe_mcache_regs->mall.p0.mcache_id_second = MCACHE_ID_UNASSIGNED; in reset_mcache_allocations()
330 per_plane_pipe_mcache_regs->mall.p0.split_location = SPLIT_LOCATION_UNDEFINED; in reset_mcache_allocations()
358 // P0 always enabled in dml2_top_mcache_build_mcache_programming()
370 params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p0.mcache_id_first = in dml2_top_mcache_build_mcache_programming()
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