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/linux/arch/hexagon/lib/
H A Dmemset.S24 #if __HEXAGON_ARCH__ < 3
28 r7 = extractu(r0, #3 , #0)
29 p0 = cmp.eq(r2, #0) define
36 if p0 jumpr r31 /* count == 0, so return */
41 p0 = tstbit(r9, #0) define
58 p0 = tstbit(r9, #1) define
60 if !p0 jump 3f /* skip initial byte store */
68 3: /* skip initial byte store */
71 p0 = tstbit(r9, #2) define
73 if !p0 jump 4f /* skip initial half store */
[all …]
H A Ddivsi3.S10 p0 = cmp.gt(r0,#-1) define
15 p3 = xor(p0,p1)
18 p0 = cmp.gtu(r3,r2) define
26 r0 = mux(p0,#0,r0)
27 p0 = or(p0,p1) define
28 if (p0.new) jumpr:nt r31
35 p0 = cmp.gtu(r6,#4) define
39 if (!p0) r6 = #3
50 if (!p0.new) r0 = add(r0,r5)
51 if (!p0.new) r2 = sub(r2,r4)
[all …]
H A Dmemcpy.S90 * prolog = prolog >> 3;
115 * epilogdws = epilog >> 3;
148 #define ifbyte p0 /* if transfer has bytes in epilog/prolog */
149 #define ifhword p0 /* if transfer has shorts in epilog/prolog */
150 #define ifword p0 /* if transfer has words in epilog/prolog */
151 #define noprolog p0 /* no prolog, xfer starts at 32byte */
153 #define noepilog p0 /* no epilog, xfer ends on 32byte boundary */
155 #define kernel1 p0 /* kernel count == 1 */
187 p0 = cmp.gtu(len, #23); /* %1, <24 */ define
194 len8 = lsr(len, #3); /* %8 < 97 */
[all …]
/linux/arch/hexagon/mm/
H A Dcopy_user_template.S19 p0 = cmp.gtu(bytes,#0) define
20 if (!p0.new) jump:nt .Ldone
26 p0 = bitsclr(r3,#7) define
27 if (!p0.new) jump:nt .Loop_not_aligned_8
32 loopcount = lsr(bytes,#3)
46 bytes -= asl(loopcount,#3)
52 p0 = bitsclr(r4,#7) define
53 if (p0.new) jump:nt .Lalign
56 p0 = bitsclr(r3,#3) define
57 if (!p0.new) jump:nt .Loop_not_aligned_4
[all …]
/linux/arch/x86/include/asm/
H A Dxor_avx.h21 BLOCK(32 * (i + 3), 3)
29 static void xor_avx_2(unsigned long bytes, unsigned long * __restrict p0, in xor_avx_2() argument
42 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_2()
44 "=m" (p0[i / sizeof(*p0)])); \ in xor_avx_2()
49 p0 = (unsigned long *)((uintptr_t)p0 + 512); in xor_avx_2()
56 static void xor_avx_3(unsigned long bytes, unsigned long * __restrict p0, in xor_avx_3() argument
72 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_3()
74 "=m" (p0[i / sizeof(*p0)])); \ in xor_avx_3()
79 p0 = (unsigned long *)((uintptr_t)p0 + 512); in xor_avx_3()
87 static void xor_avx_4(unsigned long bytes, unsigned long * __restrict p0, in xor_avx_4() argument
[all …]
/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm750-runbmc-olympus.dts52 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
236 i2c_slot2b: i2c@3 {
239 reg = <3>;
285 i2c_m2_s4: i2c@3 {
288 reg = <3>;
430 g1a-p0-0-hog {
436 g1a-p0-1-hog {
442 g1a-p0-2-hog {
448 g1a-p0-3-hog {
450 gpios = <3 0>;
[all …]
/linux/tools/testing/selftests/cgroup/
H A Dtest_cpuset_prs.sh23 CGROUP2=$(mount -t cgroup2 | head -1 | awk -e '{print $3}')
212 SETUP_A123_PARTITIONS="C1-3:P1:S+ C2-3:P1:S+ C3:P1"
216 " C0-1 . . C2-3 S+ C4-5 . . 0 A2:0-1"
217 " C0-1 . . C2-3 P1 . . . 0 "
218 " C0-1 . . C2-3 P1:S+ C0-1:P1 . . 0 "
219 " C0-1 . . C2-3 P1:S+ C1:P1 . . 0 "
220 " C0-1:S+ . . C2-3 . . . P1 0 "
221 " C0-1:P1 . . C2-3 S+ C1 . . 0 "
222 " C0-1:P1 . . C2-3 S+ C1:P1 . . 0 "
223 " C0-1:P1 . . C2-3 S+ C1:P1 . P1 0 "
[all …]
/linux/arch/hexagon/include/asm/
H A Dcmpxchg.h32 " memw_locked(%1,P0) = %2;\n" /* store into memory */ in __arch_xchg()
33 " if (!P0) jump 1b;\n" in __arch_xchg()
36 : "memory", "p0" in __arch_xchg()
63 " { P0 = cmp.eq(%0,%2);\n" \
64 " if (!P0.new) jump:nt 2f; }\n" \
65 " memw_locked(%1,p0) = %3;\n" \
66 " if (!P0) jump 1b;\n" \
70 : "memory", "p0" \
H A Datomic.h21 " memw_locked(%0,p0) = %1;\n" in arch_atomic_set()
22 " if (!P0) jump 1b;\n" in arch_atomic_set()
25 : "memory", "p0", "r6" in arch_atomic_set()
73 " %1 = "#op "(%0,%3);\n" \
119 " %1 = add(%0, %3);" in ATOMIC_OPS()
/linux/Documentation/scheduler/
H A Dsched-util-clamp.rst12 of tasks. It was introduced in v5.3 release. The CGroup support was merged in
199 +- p0 +- p3 +- p4
227 Bucket 3: [615:819]
279 p0->uclamp[UCLAMP_MIN] = 300
280 p0->uclamp[UCLAMP_MAX] = 900
285 then assuming both p0 and p1 are enqueued to the same rq, both UCLAMP_MIN
311 :ref:`Section 3 <uclamp-interfaces>` discusses the interfaces and will expand
337 3. Interfaces
382 * cpu.uclamp.min is a protection as described in :ref:`section 3-3 of cgroup
391 * cpu.uclamp.max is a limit as described in :ref:`section 3-2 of cgroup v2
[all …]
/linux/tools/memory-model/Documentation/
H A Dlitmus-tests.txt70 3 {}
72 5 P0(int *x, int *y)
105 Line 3 is the initialization section. Because the default initialization
114 The name of the first process is "P0" and that of the second "P1".
123 names are significant. The fact that both P0() and P1() have a formal
125 same global variable, also named "x". So the "int *x, int *y" on P0()
128 by reference, hence "P0(int *x, int *y)", but *never* "P0(int x, int y)".
130 P0() has no local variables, but P1() has two of them named "r0" and "r1".
145 The P0() process does "WRITE_ONCE(*x, 1)" on line 7. Because "x" is a
146 pointer in P0()'s parameter list, this does an unordered store to global
[all …]
H A Dexplanation.txt11 3. A SIMPLE EXAMPLE
116 P0()
132 Here the P0() function represents the interrupt handler running on one
135 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
163 instance, P1 might run entirely before P0 begins, in which case r1 and
164 r2 will both be 0 at the end. Or P0 might run entirely before P1
168 routines run concurrently. One possibility is that P1 runs after P0's
197 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
203 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
207 P0 stores 1 to buf before storing 1 to flag, since it executes
[all …]
/linux/arch/arm/probes/kprobes/
H A Dtest-arm.c28 "3: adr lr, 2f \n\t" \
38 TEST_ARG_MEM(15, 3f+1) \
44 "3: adr lr, 2f \n\t" \
59 TEST_RR( op s "ne r1, r",1, VAL1,", r",2, val, ", lsl #3") \ in kprobe_arm_test_cases()
60 TEST_RR( op s "cs r2, r",3, VAL1,", r",2, val, ", lsr #4") \ in kprobe_arm_test_cases()
61 TEST_RR( op s "cc r3, r",3, VAL1,", r",2, val, ", asr #5") \ in kprobe_arm_test_cases()
65 TEST_R( op s "vc r6, r",7, VAL1,", pc, lsl #3") \ in kprobe_arm_test_cases()
69 TEST_RRR( op s "hi r8, r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")\ in kprobe_arm_test_cases()
86 TEST_RR( op "eq r",1, VAL1,", r",2, val, ", lsl #3") \ in kprobe_arm_test_cases()
87 TEST_RR( op "cc r",3, VAL1,", r",2, val, ", lsr #4") \ in kprobe_arm_test_cases()
[all …]
/linux/drivers/scsi/qla4xxx/
H A Dql4_dbg.c17 printk(" 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh " in qla4xxx_dump_buffer()
106 offsetof(struct isp_reg, u2.isp4022.p0.ext_hw_conf), in qla4xxx_dump_registers()
107 readw(&ha->reg->u2.isp4022.p0.ext_hw_conf)); in qla4xxx_dump_registers()
109 offsetof(struct isp_reg, u2.isp4022.p0.port_ctrl), in qla4xxx_dump_registers()
110 readw(&ha->reg->u2.isp4022.p0.port_ctrl)); in qla4xxx_dump_registers()
112 offsetof(struct isp_reg, u2.isp4022.p0.port_status), in qla4xxx_dump_registers()
113 readw(&ha->reg->u2.isp4022.p0.port_status)); in qla4xxx_dump_registers()
115 (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_out), in qla4xxx_dump_registers()
116 readw(&ha->reg->u2.isp4022.p0.gp_out)); in qla4xxx_dump_registers()
118 (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in), in qla4xxx_dump_registers()
[all …]
/linux/arch/arm/kernel/
H A Dxscale-cp0.c22 "mrrc p0, 0, %0, %1, c0\n" in dsp_save_state()
29 "mcrr p0, 0, %0, %1, c0\n" in dsp_load_state()
126 * mar acc0, %2, %3 in cpu_has_iwmmxt()
130 * tmcrr wR0, %2, %3 in cpu_has_iwmmxt()
134 "mcrr p0, 0, %2, %3, c0\n" in cpu_has_iwmmxt()
135 "mrrc p0, 0, %0, %1, c0\n" in cpu_has_iwmmxt()
159 cp_access = xscale_cp_access_read() & ~3; in xscale_cp0_init()
/linux/drivers/media/pci/cx23885/
H A Dcx23885-f300.c9 * GPIO0 - data - P0.3 F300
10 * GPIO1 - reset - P0.2 F300
11 * GPIO2 - clk - P0.1 F300
12 * GPIO3 - busy - P0.0 F300
147 buf[3] = 0x01;/* power on */ in f300_set_voltage()
152 buf[3] = 0x01; in f300_set_voltage()
157 buf[3] = 0x00;/* power off */ in f300_set_voltage()
/linux/drivers/soc/hisilicon/
H A Dkunpeng_hccs.h10 * | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 |P0 | P1 | P2 | P3 |
158 #define HCCS_START_RETRAINING 3
166 #define HCCS_PORT_CONFIG 3
170 u8 link_fsm : 3; /* link fsm, 1: reset 2: setup 3: config 4: link-up */
/linux/drivers/parisc/
H A Deisa_enumerator.c46 return (x[3] << 24) | (x[2] << 16) | (x[1] << 8) | x[0]; in get_32()
64 vendor[3] = '\0'; in print_eisa_id()
194 len+=3; in configure_port()
205 * and at byte 3 the value to write starts.
224 get_8(buf+len+3)) | in configure_port_init()
228 outb(get_8(buf+len+3), get_16(buf+len+1)); in configure_port_init()
237 get_16(buf+len+3)) | in configure_port_init()
241 outw(cpu_to_le16(get_16(buf+len+3)), get_16(buf+len+1)); in configure_port_init()
249 get_32(buf+len+3)) | in configure_port_init()
252 outl(cpu_to_le32(get_32(buf+len+3)), get_16(buf+len+1)); in configure_port_init()
[all …]
/linux/drivers/media/usb/pwc/
H A Dpwc-dec23.c3 Decompression for chipset version 2 et 3
93 unsigned char *p0, *p8; in build_table_color() local
98 p0 = p0004[compression_mode]; in build_table_color()
102 for (j = 0; j < 8; j++, r++, p0 += 128) { in build_table_color()
107 else if (k >= 1 && k < 3) in build_table_color()
109 else if (k >= 3 && k < 6) in build_table_color()
116 bit = (r[0] >> 3) & 7; in build_table_color()
126 p0[k + 0x00] = (1 * pw) + 0x80; in build_table_color()
127 p0[k + 0x10] = (2 * pw) + 0x80; in build_table_color()
128 p0[k + 0x20] = (3 * pw) + 0x80; in build_table_color()
[all …]
/linux/drivers/gpio/
H A Dgpio-lpc32xx.c84 "p0.0", "p0.1", "p0.2", "p0.3",
85 "p0.4", "p0.5", "p0.6", "p0.7"
89 "p1.0", "p1.1", "p1.2", "p1.3",
98 "p2.0", "p2.1", "p2.2", "p2.3",
524 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; in lpc32xx_gpio_probe()
/linux/arch/mips/kernel/
H A Docteon_switch.S34 bbit0 t0, 6, 3f /* Is user access enabled? */
61 3:
116 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
247 3: /* pass 1 or CvmCtl[NOCRYPTO] set */
318 bne v0, t3, 3f /* Skip the next stuff for non-pass1 */
344 3: /* this is post-pass1 code */
437 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
454 v3mulu $10, $0, $0 /* read P0 */
457 sd $10, PT_MTP+(0*8)(sp) /* store P0 */
464 sd $10, PT_MTP+(3*8)(sp) /* store P3 */
[all …]
/linux/tools/testing/selftests/arm64/abi/
H A Dsyscall-abi-asm.S35 | (((\nw) & 3) << 13) \
46 | (((\nw) & 3) << 13) \
158 ldr z3, [x2, #3, MUL VL]
191 ldr p0, [x2]
194 wrffr p0.b
198 ldr p0, [x2, #0, MUL VL]
201 ldr p3, [x2, #3, MUL VL]
290 str z3, [x2, #3, MUL VL]
321 str p0, [x2, #0, MUL VL]
324 str p3, [x2, #3, MUL VL]
[all …]
/linux/drivers/ata/
H A Dahci_ceva.c179 /* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */ in ahci_ceva_setup()
283 if (of_property_read_u8_array(np, "ceva,p0-cominit-params", in ceva_ahci_probe()
285 dev_warn(dev, "ceva,p0-cominit-params property not defined\n"); in ceva_ahci_probe()
298 if (of_property_read_u8_array(np, "ceva,p0-comwake-params", in ceva_ahci_probe()
300 dev_warn(dev, "ceva,p0-comwake-params property not defined\n"); in ceva_ahci_probe()
313 if (of_property_read_u8_array(np, "ceva,p0-burst-params", in ceva_ahci_probe()
315 dev_warn(dev, "ceva,p0-burst-params property not defined\n"); in ceva_ahci_probe()
328 if (of_property_read_u16_array(np, "ceva,p0-retry-params", in ceva_ahci_probe()
330 dev_warn(dev, "ceva,p0-retry-params property not defined\n"); in ceva_ahci_probe()
/linux/tools/testing/selftests/arm64/signal/testcases/
H A Dsme_trap_no_sm.c18 /* SMSTART ZA ; ADDHA ZA0.S, P0/M, P0/M, Z0.S */ in sme_trap_no_sm_trigger()
32 .timeout = 3,
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-amd-ethanolx.dts48 gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
53 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
140 /*P0-P7*/ "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT",
159 //APML for P0
184 //P0 Power regulators
194 //P0/P1 Thermal diode
312 fan@3 {

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