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/linux/drivers/pci/controller/
H A Dpci-v3-semi.c3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
100 #define V3_LB_ISTAT_PCI_PERR BIT(3)
127 * This is the value applied to C/BE[3:1], with bit 0 always held 0
137 #define V3_PCI_BASE_M_PREFETCH BIT(3)
138 #define V3_PCI_BASE_M_TYPE (3 << 1)
144 #define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
145 #define V3_PCI_MAP_M_SWAP (3 << 8)
152 #define V3_LB_BASE_SWAP (3 << 8)
154 #define V3_LB_BASE_PREFETCH BIT(3)
160 #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
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/linux/arch/s390/include/asm/
H A Dfpu-insn-asm.h40 \opd = 3
103 .ifc \vxr,%v3
104 \opd = 3
204 * @v3: Vector register designated operand whose MSB is stored in
208 * RXB bit 3 (instruction bit 39) and whose remaining bits
211 * Note: In most vector instruction formats [1] V1, V2, V3, and V4 directly
212 * correspond to @v1, @v2, @v3, and @v4. But there are exceptions, such as but
219 .macro RXB rxb v1 v2=0 v3=0 v4=0
227 .if \v3 & 0x10
240 * @v3: Third vector register designated operand (for RXB)
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/linux/lib/
H A Dsiphash.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 * and HalfSipHash1-3/SipHash1-3 for an insecure PRF only suitable for
20 #define SIPROUND SIPHASH_PERMUTATION(v0, v1, v2, v3)
26 u64 v3 = SIPHASH_CONST_3; \
28 v3 ^= key->key[1]; \
34 v3 ^= b; \
43 return (v0 ^ v1) ^ (v2 ^ v3);
54 v3 ^= m; in __siphash_aligned()
69 case 3: b |= ((u64)end[2]) << 16; fallthrough; in __siphash_aligned()
87 v3 ^= m; in __siphash_unaligned()
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/linux/arch/arm64/crypto/
H A Dchacha-neon-core.S32 * registers v0-v3. It performs matrix operations on four words in parallel,
47 eor v3.16b, v3.16b, v0.16b
48 rev32 v3.8h, v3.8h
51 add v2.4s, v2.4s, v3.4s
58 eor v3.16b, v3.16b, v0.16b
59 tbl v3.16b, {v3.16b}, v12.16b
62 add v2.4s, v2.4s, v3.4s
67 // x1 = shuffle32(x1, MASK(0, 3, 2, 1))
69 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
71 // x3 = shuffle32(x3, MASK(2, 1, 0, 3))
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H A Dsm4-ce-core.S17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
42 .align 3
64 sm4ekey v3.4s, v2.4s, v27.4s;
65 sm4ekey v4.4s, v3.4s, v28.4s;
73 st1 {v0.16b-v3.16b}, [x1], #64;
80 tbl v20.16b, {v3.16b}, v24.16b
91 .align 3
107 .align 3
121 ld1 {v0.16b-v3.16b}, [x2], #64;
124 SM4_CRYPT_BLK8(v0, v1, v2, v3, v4, v5, v6, v7);
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H A Daes-ce-core.S17 bne 3f
18 mov v3.16b, v1.16b
21 ld1 {v3.4s}, [x0], #16
25 aese v0.16b, v3.16b
27 3: ld1 {v2.4s}, [x0], #16
28 subs w3, w3, #3
31 ld1 {v3.4s}, [x0], #16
34 eor v0.16b, v0.16b, v3.16b
45 bne 3f
46 mov v3.16b, v1.16b
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H A Dsm3-ce-core.S12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
65 round \ab, \s0, v12, v11, 3
89 0: ld1 {v0.16b-v3.16b}, [x1], #64
98 CPU_LE( rev32 v3.16b, v3.16b )
102 qround a, v0, v1, v2, v3, v4
103 qround a, v1, v2, v3, v4, v0
104 qround a, v2, v3, v4, v0, v1
105 qround a, v3, v4, v0, v1, v2
109 qround b, v4, v0, v1, v2, v3
110 qround b, v0, v1, v2, v3, v4
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H A Dsm4-ce-gcm-core.S18 .irp b, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31
236 /* can be the same as input v0-v3 */
240 #define RR7 v3
261 .align 3
285 /* H ^ 3 */
298 .align 3
322 ld1 {v0.16b-v3.16b}, [x2], #64
327 rbit v3.16b, v3.16b
331 * (in1) * H^3 => rr2:rr3
340 RR6, RR7, v3, RH1, RTMP6, RTMP7)
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H A Dsm4-neon-core.S140 ROUND4(3, b3, b0, b1, b2); \
238 ROUND8(3, b3, b0, b1, b2, b7, b4, b5, b6); \
259 .align 3
273 ld4 {v0.4s-v3.4s}, [x2], #64
276 SM4_CRYPT_BLK8(v0, v1, v2, v3, v4, v5, v6, v7)
278 st1 {v0.16b-v3.16b}, [x1], #64
291 ld4 {v0.4s-v3.4s}, [x2], #64
293 SM4_CRYPT_BLK4(v0, v1, v2, v3)
295 st1 {v0.16b-v3.16b}, [x1], #64
308 transpose_4x4(v0, v1, v2, v3)
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H A Dsha3-ce-core.S3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
46 ld1 { v0.1d- v3.1d}, [x0]
64 eor v3.8b, v3.8b, v28.8b
88 b 3f
90 1: tbz x3, #2, 3f // bit 2 cleared? SHA-384
100 b 3f
107 3: sub w8, w8, #1
111 eor3 v28.16b, v3.16b, v8.16b, v13.16b
124 rax1 v27.2d, v27.2d, v29.2d // bc[3]
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/linux/Documentation/devicetree/bindings/hwmon/
H A Dltc2990.txt15 2: V1-V2, V3, V4
16 3: TR1, V3, V4
17 4: TR1, V3-V4
19 6: V1-V2, V3-V4
20 7: V1, V2, V3, V4
22 The second integer defines the bits 4..3 in the control register. This
27 2: TR2, V3 or V3-V4 only per mode
28 3: All measurements per mode
35 lltc,meas-mode = <7 3>; /* V1, V2, V3, V4 */
/linux/include/uapi/linux/
H A Dnfs.h34 #define NFS_MNT3_VERSION 3
47 NFS_OK = 0, /* v2 v3 v4 */
48 NFSERR_PERM = 1, /* v2 v3 v4 */
49 NFSERR_NOENT = 2, /* v2 v3 v4 */
50 NFSERR_IO = 5, /* v2 v3 v4 */
51 NFSERR_NXIO = 6, /* v2 v3 v4 */
52 NFSERR_EAGAIN = 11, /* v2 v3 */
53 NFSERR_ACCES = 13, /* v2 v3 v4 */
54 NFSERR_EXIST = 17, /* v2 v3 v4 */
55 NFSERR_XDEV = 18, /* v3 v4 */
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/linux/Documentation/devicetree/bindings/mmc/
H A Dnvidia,tegra20-sdhci.yaml122 nvidia,pad-autocal-pull-down-offset-3v3:
127 nvidia,pad-autocal-pull-down-offset-3v3-timeout:
150 nvidia,pad-autocal-pull-up-offset-3v3:
162 nvidia,pad-autocal-pull-up-offset-3v3-timeout:
228 - const: sdmmc-3v3
232 - const: sdmmc-3v3-drv
237 - const: sdmmc-3v3-drv
257 - const: sdmmc-3v3
296 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
297 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
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/linux/arch/powerpc/lib/
H A Dxor_vmx.c33 V##_3 = V[3]; \
41 V[3] = V##_3; \
78 DEFINE(v3); in __xor_altivec_3()
84 LOAD(v3); in __xor_altivec_3()
86 XOR(v1, v3); in __xor_altivec_3()
91 v3 += 4; in __xor_altivec_3()
103 DEFINE(v3); in __xor_altivec_4()
110 LOAD(v3); in __xor_altivec_4()
113 XOR(v3, v4); in __xor_altivec_4()
114 XOR(v1, v3); in __xor_altivec_4()
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H A Dmemcpy_power7.S40 clrldi r6,r6,(64-3)
42 bf cr7*4+3,1f
54 2: bf cr7*4+1,3f
60 3: sub r5,r5,r6
170 8: bf cr7*4+3,9f
203 14: bf cr7*4+3,15f
264 bf cr7*4+3,1f
276 2: bf cr7*4+1,3f
282 3: bf cr7*4+0,4f
300 bf cr7*4+3,5f
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H A Dcopyuser_power7.S96 clrldi r6,r6,(64-3)
98 bf cr7*4+3,1f
110 2: bf cr7*4+1,3f
116 3: sub r5,r5,r6
226 8: bf cr7*4+3,9f
259 14: bf cr7*4+3,15f
318 bf cr7*4+3,1f
330 2: bf cr7*4+1,3f
336 3: bf cr7*4+0,4f
354 bf cr7*4+3,5f
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/linux/Documentation/devicetree/bindings/pci/
H A Dv3-v360epc-pci.txt1 V3 Semiconductor V360 EPC PCI bridge
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
10 first the base address of the V3 host bridge controller, 64KB
12 - interrupts: should contain a reference to the V3 error interrupt
29 operate the V3 host bridge.
34 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
37 #address-cells = <3>;
58 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
7 title: ARM Generic Interrupt Controller, version 3
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
42 Must be a single cell with a value of at least 3.
47 interrupts, 2 for interrupts in the Extended SPI range, 3 for the
55 The 3rd cell is the flags, encoded as follows:
56 bits[3:0] trigger type and level flags.
69 enum: [ 3, 4 ]
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/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-d4xx.rst20 types are MetadataId_CaptureStats (ID 3), MetadataId_CameraExtrinsics (ID 4),
29 This document implements Intel Configuration version 3 [9_].
51 2 and 3. The version number will be incremented when new fields are
77 * - __u8 Emitter mode (v3 only) (__u32 Laser mode for v1) [8_]
79 * - __u8 RFU byte (v3 only)
81 * - __u16 LED Power (v3 only)
93 - A bitmask of flags: see [3_] below
110 - Size in bytes, include ID (v1:36, v3:40)
133 * - __u16 Calibration count (v3 only)
135 * - __u8 GPIO input data (v3 only)
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/linux/arch/loongarch/lib/
H A Dxor_template.c35 void XOR_FUNC_NAME(3)(unsigned long bytes,
38 const unsigned long * __restrict v3)
46 LD_AND_XOR_LINE(v3)
48 : : [v1] "r"(v1), [v2] "r"(v2), [v3] "r"(v3) : "memory"
53 v3 += LINE_WIDTH / sizeof(unsigned long);
60 const unsigned long * __restrict v3,
69 LD_AND_XOR_LINE(v3)
72 : : [v1] "r"(v1), [v2] "r"(v2), [v3] "r"(v3), [v4] "r"(v4)
78 v3 += LINE_WIDTH / sizeof(unsigned long);
86 const unsigned long * __restrict v3,
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/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1-clockworkpi-v3.14.dts12 model = "ClockworkPi v3.14 (R-01)";
13 compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
90 regulator-name = "sys-3v3";
104 regulator-name = "aud-3v3";
110 regulator-name = "disp-3v3";
122 /* DLDO1 and ELDO1-3 are connected in parallel. */
132 regulator-name = "vcc-3v3-ext-a";
139 regulator-name = "vcc-3v3-ext-b";
146 regulator-name = "vcc-3v3-ext-c";
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/
H A Dlib_float_math.c69 double math_max3(double v1, double v2, double v3) in math_max3() argument
71 return v3 > math_max2(v1, v2) ? v3 : math_max2(v1, v2); in math_max3()
74 double math_max4(double v1, double v2, double v3, double v4) in math_max4() argument
76 return v4 > math_max3(v1, v2, v3) ? v4 : math_max3(v1, v2, v3); in math_max4()
79 double math_max5(double v1, double v2, double v3, double v4, double v5) in math_max5() argument
81 return math_max3(v1, v2, v3) > math_max2(v4, v5) ? math_max3(v1, v2, v3) : math_max2(v4, v5); in math_max5()
117 a = ((-1.0f / 3) * a + 2) * a - 2.0f / 3; in math_log()
/linux/tools/testing/selftests/powerpc/copyloops/
H A Dmemcpy_power7.S40 clrldi r6,r6,(64-3)
42 bf cr7*4+3,1f
54 2: bf cr7*4+1,3f
60 3: sub r5,r5,r6
170 8: bf cr7*4+3,9f
203 14: bf cr7*4+3,15f
264 bf cr7*4+3,1f
276 2: bf cr7*4+1,3f
282 3: bf cr7*4+0,4f
300 bf cr7*4+3,5f
[all …]
H A Dcopyuser_power7.S96 clrldi r6,r6,(64-3)
98 bf cr7*4+3,1f
110 2: bf cr7*4+1,3f
116 3: sub r5,r5,r6
226 8: bf cr7*4+3,9f
259 14: bf cr7*4+3,15f
318 bf cr7*4+3,1f
330 2: bf cr7*4+1,3f
336 3: bf cr7*4+0,4f
354 bf cr7*4+3,5f
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_encoders.c412 case 3: in amdgpu_atombios_encoder_setup_dvo()
531 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
554 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; member
601 args.v3.ucPanelMode = panel_mode; in amdgpu_atombios_encoder_setup_dig_encoder()
632 case 3: in amdgpu_atombios_encoder_setup_dig_encoder()
633 args.v3.ucAction = action; in amdgpu_atombios_encoder_setup_dig_encoder()
634 args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); in amdgpu_atombios_encoder_setup_dig_encoder()
636 args.v3.ucPanelMode = panel_mode; in amdgpu_atombios_encoder_setup_dig_encoder()
638 args.v3.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); in amdgpu_atombios_encoder_setup_dig_encoder()
640 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) in amdgpu_atombios_encoder_setup_dig_encoder()
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