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/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,cmt.yaml202 clocks = <&cpg CPG_MOD 329>;
205 resets = <&cpg 329>;
/linux/include/dt-bindings/gce/
H A Dmt8183-gce.h160 #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329
H A Dmt6779-gce.h170 #define CMDQ_EVENT_ISP_TSF_DONE 329
H A Dmt8192-gce.h238 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329
/linux/include/dt-bindings/clock/
H A Drk3036-cru.h63 #define PCLK_GRF 329
H A Dexynos5250.h133 #define CLK_TZPC5 329
H A Drk3188-cru-common.h81 #define PCLK_SPI1 329
H A Drk3128-cru.h102 #define PCLK_GRF 329
H A Drk3228-cru.h101 #define PCLK_GRF 329
H A Dexynos4.h167 #define CLK_SPI2 329
H A Drv1108-cru.h148 #define HCLK_RKVENC 329
H A Dqcom,gcc-apq8084.h338 #define GCC_PCIE_1_CFG_AHB_CLK 329
H A Drk3368-cru.h113 #define PCLK_GRF 329
H A Drk3328-cru.h190 #define HCLK_PERI_PRE 329
H A Dpx30-cru.h152 #define PCLK_UART1 329
H A Drk3288-cru.h121 #define PCLK_GRF 329
H A Dimx8mp-clock.h337 #define IMX8MP_CLK_MEDIA_LDB_ROOT 329
H A Dtegra210-car.h363 /* 329 */
/linux/Documentation/devicetree/bindings/net/
H A Damd-xgbe.txt62 <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
/linux/Documentation/devicetree/bindings/scsi/
H A Dhisilicon-sas.txt84 <329 4>,<333 4>,<334 4>,/* phy7 */
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8dxl-ss-adma.dtsi89 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu981_regs.h440 #define av1_pp_out_c_stride AV1_DEC_REG(329, 0, 0xffff)
441 #define av1_pp_out_y_stride AV1_DEC_REG(329, 16, 0xffff)
/linux/drivers/net/ethernet/intel/ice/
H A Dice_flex_type.h24 #define ICE_MAC_IPV4_GTPU 329
/linux/tools/perf/arch/mips/entry/syscalls/
H A Dsyscall_n64.tbl340 # 329 through 423 are reserved to sync up with other architectures
/linux/drivers/clk/renesas/
H A Dr8a7792-cpg-mssr.c97 DEF_MOD("cmt1", 329, R8A7792_CLK_R),

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