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/linux/drivers/media/v4l2-core/
H A Dv4l2-vp9.c17 { 137, 30, 42, 148, 151, 207, 70, 52, 91 }, /*left = dc */
20 { 91, 30, 32, 116, 121, 186, 93, 86, 94 }, /*left = d45 */
35 { 52, 30, 74, 113, 130, 175, 51, 64, 58 }, /*left = d207*/
52 { 62, 30, 23, 158, 200, 207, 59, 57, 50 }, /*left = h */
53 { 67, 30, 29, 84, 86, 191, 102, 91, 59 }, /*left = d45 */
91 { 55, 30, 18, 122, 79, 179, 44, 88, 116 }, /*left = d63 */
96 { 47, 25, 17, 175, 222, 220, 24, 30, 86 }, /*left = h */
99 { 49, 30, 35, 141, 70, 168, 82, 40, 115 }, /*left = d117*/
230 { 12, 30, 81 },
331 { 30, 44, 136 },
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
H A Dgk20a.c41 /* 684 */ { 1391884, -17078, -274, -60, -1526, 30},
54 int mv; in gk20a_volt_get_cvb_voltage() local
56 mv = DIV_ROUND_CLOSEST(coef->c2 * speedo, s_scale); in gk20a_volt_get_cvb_voltage()
57 mv = DIV_ROUND_CLOSEST((mv + coef->c1) * speedo, s_scale) + coef->c0; in gk20a_volt_get_cvb_voltage()
58 return mv; in gk20a_volt_get_cvb_voltage()
70 int cvb_mv, mv; in gk20a_volt_get_cvb_t_voltage() local
74 mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 + in gk20a_volt_get_cvb_t_voltage()
76 mv = DIV_ROUND_CLOSEST(mv * temp, t_scale) + cvb_mv; in gk20a_volt_get_cvb_t_voltage()
77 return mv; in gk20a_volt_get_cvb_t_voltage()
84 int mv; in gk20a_volt_calc_voltage() local
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_aldebaran.h68 #define FEATURE_CLK_CG_BIT 30
292 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
293 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
342 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed]
343 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed]
344 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed]
347 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed]
348 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed]
349 int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed]
353 int16_t DcBtcMin; // mV [signed]
[all …]
H A Dsmu13_driver_if_v13_0_7.h79 #define FEATURE_FAN_CONTROL_BIT 30
872 uint16_t InitGfx; // In mV(Q2) , should be 0?
873 uint16_t InitSoc; // In mV(Q2)
874 uint16_t InitU; // In Mv(Q2) not applicable
928 uint16_t DcTol; // mV Q2
929 uint16_t DcBtcGb; // mV Q2
931 uint16_t DcBtcMin; // mV Q2
932 uint16_t DcBtcMax; // mV Q2
941 uint16_t VInversion; // in mV Q2
1004 …uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV…
[all …]
H A Dsmu11_driver_if_arcturus.h90 #define FEATURE_SPARE_30_BIT 30
497 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
504 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
505 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
506 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
507 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
526 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
583 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
588 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2
589 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2
[all …]
H A Dsmu14_driver_if_v14_0.h76 #define FEATURE_GFX_DCS_BIT 30
757 uint16_t VddGfxVmax; // in mV
820 uint16_t VddGfxVmax; // in mV
964 uint16_t InitGfx; // In mV(Q2) , should be 0?
965 uint16_t InitSoc; // In mV(Q2)
966 uint16_t InitVddIoMem; // In mV(Q2) MemVdd
967 uint16_t InitVddCiMem; // In mV(Q2) VMemP
1019 uint16_t DcTol; // mV Q2
1020 uint16_t DcBtcGb; // mV Q2
1022 uint16_t DcBtcMin; // mV Q2
[all …]
H A Dsmu11_driver_if_navi10.h104 #define FEATURE_VR1HOT_BIT 30
558 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
559 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
569 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
570 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
574 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
575 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
576 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
577 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
603 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h109 #define FEATURE_VR1HOT_BIT 30
633 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
636 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2)
646 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
647 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
649 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
650 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
652 uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC
659 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
660 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
[all …]
H A Dsmu13_driver_if_v13_0_0.h78 #define FEATURE_FAN_CONTROL_BIT 30
863 uint16_t InitGfx; // In mV(Q2) , should be 0?
864 uint16_t InitSoc; // In mV(Q2)
865 uint16_t InitU; // In Mv(Q2)
919 uint16_t DcTol; // mV Q2
920 uint16_t DcBtcGb; // mV Q2
922 uint16_t DcBtcMin; // mV Q2
923 uint16_t DcBtcMax; // mV Q2
932 uint16_t VInversion; // in mV Q2
995 …uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV…
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/linux/Documentation/devicetree/bindings/power/supply/
H A Dmediatek,mt6370-charger.yaml50 VBUS voltage with lower accuracy (+-75mV) but higher measure
53 VBUS voltage with higher accuracy (+-30mV) but lower measure
/linux/drivers/cpufreq/
H A Darmada-37xx-cpufreq.c47 #define ARMADA_37XX_NB_VDD_EN BIT(30)
58 #define ARMADA_37XX_AVS_ENABLE BIT(30)
77 /* AVS value for the corresponding voltage (in mV) */
209 * - L1 voltage should be about 100mv smaller than L0 voltage
210 * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
238 * If L0 voltage is smaller than 1000mv, then all VDD sets in armada37xx_cpufreq_avs_configure()
263 * L1 voltage is equal to L0 voltage - 100mv and it must be in armada37xx_cpufreq_avs_configure()
264 * larger than 1000mv in armada37xx_cpufreq_avs_configure()
272 * L2 & L3 voltage is equal to L0 voltage - 150mv and it must in armada37xx_cpufreq_avs_configure()
273 * be larger than 1000mv in armada37xx_cpufreq_avs_configure()
H A Dlonghaul.c455 minmult = 30; in longhaul_get_ranges()
557 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) { in longhaul_setup_voltagescaling()
559 minvid.mV/1000, minvid.mV%1000, in longhaul_setup_voltagescaling()
560 maxvid.mV/1000, maxvid.mV%1000); in longhaul_setup_voltagescaling()
564 if (minvid.mV == maxvid.mV) { in longhaul_setup_voltagescaling()
566 maxvid.mV/1000, maxvid.mV%1000); in longhaul_setup_voltagescaling()
573 maxvid.mV/1000, maxvid.mV%1000, in longhaul_setup_voltagescaling()
574 minvid.mV/1000, minvid.mV%1000, in longhaul_setup_voltagescaling()
610 pr_info("f: %d kHz, index: %d, vid: %d mV\n", in longhaul_setup_voltagescaling()
611 speed, j, vid.mV); in longhaul_setup_voltagescaling()
H A Dpowernow-k8.h54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
121 #define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */
129 #define IRT_SHIFT 30
/linux/drivers/iio/light/
H A Dcm3605.c83 dev_dbg(cm3605->dev, "read %d mV from ADC\n", res); in cm3605_get_lux()
86 * AOUT has an offset of ~30mV then linear at dark in cm3605_get_lux()
88 * (1550 mV) so scale the returned value to this interval in cm3605_get_lux()
91 if (res < 30) in cm3605_get_lux()
97 lux = res - 30; in cm3605_get_lux()
/linux/drivers/regulator/
H A Dqcom_rpm-regulator.c27 struct request_member mV; /* used if voltage is in mV */ member
67 .mV = { 0, 0x00000FFF, 0 },
71 .pf = { 0, 0xC0000000, 30 },
78 .mV = { 0, 0x00000FFF, 0 },
82 .pf = { 0, 0xC0000000, 30 },
100 .mV = { 0, 0x00000FFF, 0 },
168 REGULATOR_LINEAR_RANGE( 750000, 30, 89, 12500),
180 REGULATOR_LINEAR_RANGE( 750000, 30, 89, 12500),
211 const struct request_member *req = &parts->mV; in rpm_reg_set_mV_sel()
271 const struct request_member *req = &parts->mV; in rpm_reg_mV_enable()
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h92 /* MV Vector Valid */
94 /* MV Flag Valid */
179 /* Current MV Flag Status Pointer for Channel n. (Read only) */
190 * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each)
549 #define TW5864_TEST_ADLOOP_EN BIT(30)
578 * Bit[32:30] ch10
587 #define TW5864_ADPCM_ENC_XX_PTR2_SHIFT 30
590 /* ADPCM_ENC_WR_PTR[50:30] */
595 /* ADPCM_ENC_RD_PTR[50:30] */
730 * 1 30% higher current
[all …]
/linux/sound/soc/codecs/
H A Dtlv320adc3xxx.c100 #define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30)
352 { 28, 0x00 }, { 29, 0x02 }, { 30, 0x01 }, { 31, 0x00 },
645 "0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "10
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-adc-mt636013 higher measure range(1~22mV)
20 Indicated MT6360 VBUS ADC with higher accuracy(+-30mA)
/linux/drivers/phy/marvell/
H A Dphy-pxa-usb.c37 #define UTMI_CTRL_SUSPEND_SET1 (1 << 30)
42 #define UTMI_CTRL_INPKT_DELAY_SHIFT 30
323 phy_create_lookup(pxa_usb_phy->phy, "usb", "mv-udc"); in pxa_usb_phy_probe()
325 phy_create_lookup(pxa_usb_phy->phy, "usb", "mv-otg"); in pxa_usb_phy_probe()
/linux/drivers/iio/accel/
H A Dadis16209.c150 *val2 = 305180; /* 0.30518 mV */ in adis16209_read_raw()
153 *val2 = 610500; /* 0.6105 mV */ in adis16209_read_raw()
250 .read_delay = 30,
/linux/arch/arm/boot/dts/rockchip/
H A Drk3128-xpi-3128.dts228 * As per schematics vdd_log is minimum 900 mV, maximum 1400 mV.
232 * sure here that the voltage never drops below 1050 mV.
238 pwm-dutycycle-range = <30 100>;
/linux/include/uapi/linux/
H A Dfb.h102 #define FB_ACCEL_CT_6555x 30 /* C&T 6555x */
117 #define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */
140 #define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */
142 #define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */
144 #define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgm20b.c77 #define GPCPLL_DVFS1_EN_DFS_CAL_SHIFT 30
79 #define GPCPLL_DVFS1_EN_DFS_CAL_BIT BIT(30)
196 /* Work with mv as uv would likely trigger an overflow */ in gm20b_dvfs_calc_det_coeff()
197 s32 mv = DIV_ROUND_CLOSEST(uv, 1000); in gm20b_dvfs_calc_det_coeff() local
200 coeff = DIV_ROUND_CLOSEST(mv * p->coeff_slope, 1000) + p->coeff_offs; in gm20b_dvfs_calc_det_coeff()
943 #define FUSE_RESERVED_CALIB0_FUSE_REV_SHIFT 30
963 /* Integer part in mV + fractional part in uV */ in gm20b_clk_init_fused_params()
969 /* Integer part in mV + fractional part in 100uV */ in gm20b_clk_init_fused_params()
/linux/tools/testing/selftests/drivers/platform/x86/intel/ifs/
H A Dtest_ifs.sh122 mv -f "$IMG_PATH"/"$IMAGE_NAME"_origin "$IMG_PATH"/"$IMAGE_NAME"
209 INTERVAL_TIME=30;
301 do_cmd "mv -f ${IMG_PATH}/${IMAGE_NAME} ${IMG_PATH}/${IMAGE_NAME}_origin"
317 do_cmd "mv -f ${IMG_PATH}/${IMAGE_NAME}_origin ${IMG_PATH}/${IMAGE_NAME}"
/linux/drivers/gpu/drm/msm/registers/display/
H A Dmdp4.xml80 <bitfield name="PIPE7" low="28" high="30" type="mdp_mixer_stage_id"/>
99 <bitfield name="OVERLAY2_DONE" pos="30" type="boolean"/>
195 <array offset="0x400" name="MV" length="9" stride="4">
264 <array offset="0x400" name="MV" length="9" stride="4">
320 <bitfield name="FRAME_FORMAT" low="29" high="30" type="mdp4_frame_format"/>
344 <array offset="0x400" name="MV" length="9" stride="4">
376 <bitfield name="END" low="16" high="30" type="uint"/>

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