| /linux/net/wireless/tests/ |
| H A D | chan.c | 44 .desc = "identical 20 MHz",
53 .desc = "identical 40 MHz",
62 .desc = "identical 80 MHz",
71 .desc = "identical 160 MHz",
80 .desc = "identical 320 MHz",
89 .desc = "20 MHz in 320 MHz\n",
103 .desc = "different 20 MHz",
116 .desc = "different primary 320 MHz",
130 .desc = "matching primary 160 MHz",
134 .center_freq1 = 6475 + 30,
[all …]
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| /linux/arch/powerpc/boot/dts/ |
| H A D | ac14xx.dts | 26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
145 bus-frequency = <80000000>; /* 80 MHz ips bus */
174 at24@30 {
262 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
263 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
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| /linux/drivers/clk/ |
| H A D | clk-tps68470.c | 41 * frequency range of 3 MHz to 27 MHz by a programmable
44 * of 4 MHz to 64 MHz in increments of 0.1 MHz.
46 * hclk_# = osc_in * (((plldiv*2)+320) / (xtaldiv+30)) * (1 / 2^postdiv)
49 * PLL_REF_CLK = input clk / XTALDIV[7:0] + 30)
53 * BOOST should be as close as possible to 2Mhz
56 * BUCK should be as close as possible to 5.2Mhz
60 * 20Mhz 170 32 1 19.2Mhz
61 * 20Mhz 170 40 1 20Mhz
62 * 20Mhz 170 80 1 24Mhz
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| H A D | clk-gemini.c | 29 #define PLL_OSC_SEL BIT(30)
132 /* We support 33 and 66 MHz */ in gemini_pci_determine_rate()
229 /* Manual says to always set BIT 30 (CPU1) to 1 */ in gemini_reset()
354 * This clock is supposed to be 27MHz as this is an exact multiple in gemini_clk_probe()
433 * XTAL is the crystal oscillator, 60 or 30 MHz selected from in gemini_cc_init()
441 pr_debug("main crystal @%lu MHz\n", freq / 1000000); in gemini_cc_init()
446 /* If we run on 30 MHz crystal we have to multiply with two */ in gemini_cc_init()
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| /linux/include/linux/mfd/ |
| H A D | si476x-platform.h | 72 SI476X_ICIN_IC_LINK = 30,
80 SI476X_ICIP_IC_LINK = 30,
87 SI476X_ICON_IC_LINK = 30,
94 SI476X_ICOP_IC_LINK = 30,
202 * SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
203 * SI476X_XTAL_36P4_MHZ - 36.4 Mhz
204 * SI476X_XTAL_37P8_MHZ - 37.8 Mhz
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| /linux/drivers/media/dvb-frontends/ |
| H A D | s5h1432.c | 90 /* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */ in s5h1432_set_channel_bandwidth()
199 msleep(30); in s5h1432_set_frontend()
201 msleep(30); in s5h1432_set_frontend()
223 msleep(30); in s5h1432_set_frontend()
225 msleep(30); in s5h1432_set_frontend()
269 /*Set 3.3MHz as default IF frequency */ in s5h1432_init()
285 msleep(30); in s5h1432_init()
364 .frequency_min_hz = 177 * MHz,
365 .frequency_max_hz = 858 * MHz,
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| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_kunit_edid.h | 41 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
46 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
73 * This edid is intentionally broken with the 100MHz limit. It's meant
117 * DMT 0x04: 640x480 59.940476 Hz 4:3 31.469 kHz 25.175000 MHz
120 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
125 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
139 * VIC 16: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz
148 * Maximum TMDS clock: 100 MHz
230 * DMT 0x04: 640x480 59.940476 Hz 4:3 31.469 kHz 25.175000 MHz
233 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
[all …]
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| /linux/drivers/watchdog/ |
| H A D | sc520_wdt.c | 84 * char to /dev/watchdog every 30 seconds.
87 #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */
108 #define WDT_EXP_SEL_01 0x0001 /* [01] Time-out = 496 us (with 33 Mhz clk). */
109 #define WDT_EXP_SEL_02 0x0002 /* [02] Time-out = 508 ms (with 33 Mhz clk). */
110 #define WDT_EXP_SEL_03 0x0004 /* [03] Time-out = 1.02 s (with 33 Mhz clk). */
111 #define WDT_EXP_SEL_04 0x0008 /* [04] Time-out = 2.03 s (with 33 Mhz clk). */
112 #define WDT_EXP_SEL_05 0x0010 /* [05] Time-out = 4.07 s (with 33 Mhz clk). */
113 #define WDT_EXP_SEL_06 0x0020 /* [06] Time-out = 8.13 s (with 33 Mhz clk). */
114 #define WDT_EXP_SEL_07 0x0040 /* [07] Time-out = 16.27s (with 33 Mhz clk). */
115 #define WDT_EXP_SEL_08 0x0080 /* [08] Time-out = 32.54s (with 33 Mhz clk). */
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| /linux/drivers/net/wireless/ath/ath10k/ |
| H A D | rx_desc.h | 44 RX_ATTENTION_FLAGS_FCS_ERR = BIT(30),
371 #define RX_MPDU_END_INFO0_DECRYPT_ERR BIT(30)
586 #define RX_MSDU_END_INFO0_PRE_DELIM_ERR BIT(30)
767 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
771 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
775 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
779 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
783 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
787 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
791 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
[all …]
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| /linux/drivers/clk/ingenic/ |
| H A D | jz4760-cgu.c | 20 #define MHZ (1000 * 1000) macro
63 /* The frequency after the N divider must be between 1 and 50 MHz. */ in jz4760_cgu_calc_m_n_od()
64 n = parent_rate / (1 * MHZ); in jz4760_cgu_calc_m_n_od()
69 rate /= MHZ; in jz4760_cgu_calc_m_n_od()
70 parent_rate /= MHZ; in jz4760_cgu_calc_m_n_od()
243 .mux = { CGU_REG_LPCDR, 30, 1 },
260 .mux = { CGU_REG_PCMCDR, 30, 2 },
268 .mux = { CGU_REG_I2SCDR, 30, 2 },
275 .mux = { CGU_REG_USBCDR, 30, 2 },
382 .gate = { CGU_REG_LCR, 30, false, 150 },
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| /linux/drivers/clk/mvebu/ |
| H A D | dove.c | 26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
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| H A D | armada-375.c | 29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
172 { "crypto1_enc", NULL, 30 },
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| /linux/sound/soc/codecs/ |
| H A D | es83xx-dsm-common.h | 169 #define LINEIN_GAIN_30db 0x0a /* gain = +30db */
253 #define ADC_ALC_MINGAIN_30db 0x1c /* gain = +30db */
330 #define ADC_ALC_NGTHLD_m30db 0x1f /* Threshold = -30db */
376 * 0 - 19.2MHz
377 * 1 - 24MHz
378 * 2 - 12.288MHz
379 * F - Default for 19.2MHz
382 * 0 - 4.8MHz
383 * 1 - 2.4MHz
384 * 2 - 2.304MHz
[all …]
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| /linux/drivers/video/fbdev/ |
| H A D | valkyriefb.h | 79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
[all …]
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | rockchip,rk3399-dwc3.yaml | 27 Controller reference clock, must to be 24 MHz
29 Controller suspend clock, must to be 24 MHz or 32 KHz
31 Master/Core clock, must to be >= 62.5 MHz for SS
32 operation and >= 30MHz for HS operation
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| H A D | rockchip,dwc3.yaml | 57 Controller reference clock, must to be 24 MHz
59 Controller suspend clock, must to be 24 MHz or 32 KHz
61 Master/Core clock, must to be >= 62.5 MHz for SS
62 operation and >= 30MHz for HS operation
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| /linux/drivers/ata/ |
| H A D | pata_hpt37x.c | 3 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
26 #define DRV_VERSION "0.6.30"
56 * 30 PIO_MST enable. If set, the chip is in bus master mode during
595 * @freq: Reported frequency in MHz
598 * and 3 for 66Mhz)
604 return 0; /* 33Mhz slot */ in hpt37x_clock_slot()
606 return 1; /* 40Mhz slot */ in hpt37x_clock_slot()
608 return 2; /* 50Mhz slot */ in hpt37x_clock_slot()
609 return 3; /* 60Mhz slot */ in hpt37x_clock_slot()
688 freq = (fcnt * base) / 192; /* in MHz */ in hpt37x_pci_clock()
[all …]
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| /linux/drivers/clk/ti/ |
| H A D | clk-33xx.c | 19 "clk-24mhz-clkctrl:0000:0",
152 "l3-aon-clkctrl:0000:30",
187 { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
207 { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
241 DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
243 DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
244 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
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| /linux/drivers/phy/ti/ |
| H A D | phy-ti-pipe3.c | 75 #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
76 #define MEM_DLL_TRIM_SHIFT 30
79 #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
80 #define MEM_DLL_PHINT_RATE_SHIFT 30
187 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
188 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
189 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
190 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
191 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
192 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
[all …]
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| /linux/arch/arm/mach-rockchip/ |
| H A D | pm.c | 143 * source. Therefore set 30ms on a 32kHz clock for pmic in rk3288_slp_mode_set()
144 * stabilization. Similar 30ms on 24MHz for the other in rk3288_slp_mode_set()
147 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30); in rk3288_slp_mode_set()
151 osc_disable ? 32 * 30 : 0); in rk3288_slp_mode_set()
163 /* 30ms on a 24MHz clock for pmic stabilization */ in rk3288_slp_mode_set()
164 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30); in rk3288_slp_mode_set()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smu9_driver_if.h | 121 uint16_t Freq; /* in MHz */
320 /* ACG Frequency Table, in Mhz */
330 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
331 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
377 uint16_t avgPsmCount[30];
378 uint16_t minPsmCount[30];
379 float avgPsmVoltage[30];
380 float minPsmVoltage[30];
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| /linux/Documentation/devicetree/bindings/clock/st/ |
| H A D | st,quadfs.txt | 5 or 660MHz (from a 30MHz oscillator input) as the input to the digital
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| /linux/Documentation/fb/ |
| H A D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
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| /linux/Documentation/driver-api/media/drivers/ |
| H A D | saa7134-devel.rst | 14 - 32.11 MHz -> .audio_clock=0x187de7
15 - 24.576MHz -> .audio_clock=0x200000 (xtal * .audio_clock = 51539600)
17 Some details about 30/34/35:
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| /linux/drivers/video/fbdev/sis/ |
| H A D | initdef.h | 110 #define SetSimuScanMode 0x0001 /* CR 30 */
171 #define SupportRAMDAC2 0x0040 /* All (<= 100Mhz) */
172 #define SupportRAMDAC2_135 0x0100 /* All except DH (<= 135Mhz) */
173 #define SupportRAMDAC2_162 0x0200 /* B, C (<= 162Mhz) */
174 #define SupportRAMDAC2_202 0x0400 /* C (<= 202Mhz) */
278 30x: 0: Bridge scales / 1: Bridge does not scale = Panel scales (if possible)
305 #define SetToLCDA 0x02 /* LCD channel A (301C/302B/30x(E)LV and 650+LVDS only) */
308 #define EnableSiSYPbPr 0x08 /* Enable YPbPr mode (30xLV/301C only) */
309 #define EnableYPbPr525i 0x00 /* Enable 525i YPbPr mode (30xLV/301C only) (mask 0x30) */
310 #define EnableYPbPr525p 0x10 /* Enable 525p YPbPr mode (30xLV/301C only) (mask 0x30) */
[all …]
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