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/linux/Documentation/admin-guide/media/
H A Dgspca-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - gspca_main: main driver
9 - gspca\_\ *driver*: subdriver module with *driver* as follows
19 spca501 040a:0002 Kodak DVC-325
24 spca500 041e:400a Creative PC-CAM 300
25 sunplus 041e:400b Creative PC-CAM 600
26 sunplus 041e:4012 PC-Cam350
41 sq930x 041e:4038 Creative Joy-IT
69 sn9c20x 0458:704c Genius i-Look 1321
70 sn9c20x 045e:00f4 LifeCam VX-6000 (SN9C20x + OV9650)
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
H A Dfsl-ls1028a-qds-13bb.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
9 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 slot1_sgmii: ethernet-phy@2 {
22 compatible = "ethernet-phy-ieee802.3-c45";
27 phy-handle = <&slot1_sgmii>;
[all …]
H A Dfsl-ls1028a-qds-7777.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 slot1_sxgmii0: ethernet-phy@0 {
22 compatible = "ethernet-phy-ieee802.3-c45";
25 slot1_sxgmii1: ethernet-phy@1 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
H A Dfsl-lx2162a-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2023 Josua Mayer <josua@solid-run.com>
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
10 #include "fsl-lx2162a-sr-som.dtsi"
14 compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
35 stdout-path = "serial0:115200n8";
39 compatible = "gpio-leds";
41 led_sfp_at: led-sfp-at {
43 default-state = "off";
[all …]
H A Dfsl-ls2080a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
15 #include "fsl-ls2080a.dtsi"
16 #include "fsl-ls208xa-rdb.dtsi"
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
24 stdout-path = "serial1:115200n8";
29 phy-handle = <&mdio2_phy1>;
30 phy-connection-type = "10gbase-r";
34 phy-handle = <&mdio2_phy2>;
[all …]
H A Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
H A Dfsl-lx2160a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2018-2020 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/linux/drivers/net/phy/
H A Dqt2025.rs1 // SPDX-License-Identifier: GPL-2.0
8 //! and firmware can be downloaded on the EN-9320SFP+ support site.
10 //! The QT2025 PHY integrates an Intel 8051 micro-controller.
17 reg::{Mmd, C45},
32 firmware: ["qt2025-2.0.3.3.fw"],
42 fn probe(dev: &mut phy::Device) -> Result<()> { in probe()
45 let hw_rev = dev.read(C45::new(Mmd::PMAPMD, 0xd001))?; in probe()
50 // `MICRO_RESETN`: hold the micro-controller in reset while configuring. in probe()
51 dev.write(C45::new(Mmd::PMAPMD, 0xc300), 0x0000)?; in probe()
52 // `SREFCLK_FREQ`: configure clock frequency of the micro-controller. in probe()
[all …]
H A Dmicrochip_t1s.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Microchip 10BASE-T1S PHYs
37 * W 0x1F 0x008B 0x0404 ------
41 * W 0x1F 0x0099 0x7F80 ------
186 cfg_results[3] = (cfg_params[3] & 0xC0C0) | in lan865x_setup_cfgparam()
201 …Documents/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8650-1-Configuration-60001760.… in lan865x_revb0_config_init()
220 /* The chip completes a reset in 3us, we might get here earlier than in lan867x_revb1_config_init()
234 return -ENODEV; in lan867x_revb1_config_init()
239 …aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf in lan867x_revb1_config_init()
259 * - always reports link up in lan86xx_read_status()
[all …]
H A Dbcm87xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2012 Cavium, Inc.
22 * broadcom,c45-reg-init property stored in the of_node for the phydev.
24 * broadcom,c45-reg-init = <devid reg mask value>,...;
28 * devid: which sub-device to use.
30 * mask: if non-zero, ANDed with existing register value.
40 if (!phydev->mdio.dev.of_node) in bcm87xx_of_reg_init()
43 paddr = of_get_property(phydev->mdio.dev.of_node, in bcm87xx_of_reg_init()
44 "broadcom,c45-reg-init", &len); in bcm87xx_of_reg_init()
52 while (paddr + 3 < paddr_end) { in bcm87xx_of_reg_init()
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/linux/Documentation/devicetree/bindings/net/
H A Dbroadcom-bcm87xx.txt5 "ethernet-phy-ieee802.3-c45"
9 - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell
18 ethernet-phy@5 {
20 compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
21 interrupt-parent = <&gpio>;
28 broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
H A Dmdio-mux-mmioreg.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
H A Dmarvell,aquantia.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
16 This can be done and is implemented by OEM in 3 different way:
17 - Attached SPI flash directly to the PHY with the firmware. The PHY
19 - Read from a dedicated partition on system NAND declared in an
21 - Manually provided firmware loaded from a file in the filesystem.
24 - $ref: ethernet-phy.yaml#
31 - ethernet-phy-id03a1.b445
[all …]
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
/linux/rust/kernel/net/phy/
H A Dreg.rs1 // SPDX-License-Identifier: GPL-2.0
24 /// C22 and C45 PHY registers.
32 /// // read C45 PMA/PMD control 1 register
33 /// dev.read(C45::new(Mmd::PMAPMD, 0));
38 /// // Checks the link status as reported by registers in the C45 namespace
40 /// dev.genphy_read_status::<phy::C45>();
45 fn read(&self, dev: &mut Device) -> Result<u16>; in read()
48 fn write(&self, dev: &mut Device, val: u16) -> Result; in write()
51 fn read_status(dev: &mut Device) -> Result<u16>; in read_status()
67 /// Auto-negotiation advertisement.
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779f0-spider-ethernet.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Spider Ethernet sub-board
15 label = "ethernet-sub-board";
25 power-source = <1800>;
31 power-source = <1800>;
37 power-source = <1800>;
42 pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
43 pinctrl-names = "default";
46 ethernet-ports {
47 #address-cells = <1>;
[all …]
H A Dwhite-hawk-ethernet.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the White Hawk RAVB/Ethernet(1000Base-T1)
4 * sub-board
17 pinctrl-0 = <&avb1_pins>;
18 pinctrl-names = "default";
19 phy-handle = <&avb1_phy>;
23 #address-cells = <1>;
24 #size-cells = <0>;
26 reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
27 reset-post-delay-us = <4000>;
[all …]
H A Dr8a779f4-s4sk.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4 Starter Kit board
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
13 model = "R-Car S4 Starter Kit board";
30 stdout-path = "serial0:921600n8";
45 vcc_sdhi: regulator-vcc-sdhi {
46 compatible = "regulator-fixed";
47 regulator-name = "SDHI Vcc";
48 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
86 3 0 0xf 0xffdf0000 0x00008000>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
[all …]
H A Db4860qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4860si-pre.dtsi"
50 board-control@3,0 {
51 compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
58 phy-handle = <&phy_sgmii_1e>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_1f>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&phy_xaui_slot1>;
69 phy-connection-type = "xgmii";
[all …]
H A Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040-mcbin.dtsi"
11 model = "Marvell 8040 MACCHIATOBin Double-shot";
12 compatible = "marvell,armada8040-mcbin-doubleshot",
13 "marvell,armada8040-mcbin", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-381-netgear-gs110emx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 /dts-v1/;
5 #include "armada-385.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
14 /* So that mvebu u-boot can update the MAC addresses */
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-0 = <&front_button_pins>;
[all …]
/linux/drivers/net/mdio/
H A Dmdio-cavium.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009-2016 Cavium, Inc.
11 #include "mdio-cavium.h"
18 if (m == p->mode) in cavium_mdiobus_set_mode()
21 smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
22 smi_clk.s.mode = (m == C45) ? 1 : 0; in cavium_mdiobus_set_mode()
24 oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
25 p->mode = m; in cavium_mdiobus_set_mode()
35 cavium_mdiobus_set_mode(p, C45); in cavium_mdiobus_c45_addr()
39 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
[all …]

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