Searched +full:2 +full:f120000 (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)37 enum: [ 1, 2 ]40 enum: [ 1, 2 ]50 The 2nd cell contains the interrupt INTID.ID field.56 2 = high-to-low edge triggered108 enum: [ 1, 2 ]111 enum: [ 1, 2 ]159 enum: [ 1, 2 ]162 enum: [ 1, 2 ]236 irs@2f1a0000 {[all …]
57 reg-shift = <2>;67 reg-shift = <2>;77 reg-shift = <2>;87 reg-shift = <2>;96 cache-level = <2>;120 #gpio-cells = <2>;121 #interrupt-cells = <2>;395 usbotg: usb@3f120000 {
17 #address-cells = <2>;18 #size-cells = <2>;38 #address-cells = <2>;50 cache-level = <2>;64 cpu2: cpu@2 {91 cache-level = <2>;260 #address-cells = <2>;261 #size-cells = <2>;397 #gpio-cells = <2>;399 #interrupt-cells = <2>;[all …]
26 #address-cells = <2>;27 #size-cells = <2>;44 #address-cells = <2>;61 cache-level = <2>;80 cpu2: cpu@2 {122 cache-level = <2>;439 #address-cells = <2>;440 #size-cells = <2>;546 qcom,remote-pid = <2>;557 #interrupt-cells = <2>;[all …]
18 #address-cells = <2>;19 #size-cells = <2>;39 #cooling-cells = <2>;56 #cooling-cells = <2>;61 cache-level = <2>;117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |123 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |134 #address-cells = <2>;[all …]