Searched +full:2 +full:c010000 (Results 1 – 6 of 6) sorted by relevance
33 enum: [ 0, 1, 2 ]35 enum: [ 1, 2 ]47 interrupts, 2 for interrupts in the Extended SPI range, 3 for the50 The 2nd cell contains the interrupt number for the interrupt type.86 minItems: 2127 minItems: 2128 maxItems: 2138 maxItems: 2227 minItems: 2228 maxItems: 2[all...]
10 memtimer: timer@2a810000 {18 frame@2a830000 {25 mailbox: mhu@2b1f0000 {36 smmu_gpu: iommu@2b400000 {48 smmu_pcie: iommu@2b500000 {59 smmu_etr: iommu@2b600000 {70 gic: interrupt-controller@2c010000 {446 port@2 {447 reg = <2>;[all...]
17 #address-cells = <2>;18 #size-cells = <2>;29 /* We have 2 clusters having 4 Cortex-A53 cores each */36 #cooling-cells = <2>;45 #cooling-cells = <2>;48 cpu2: cpu@2 {54 #cooling-cells = <2>;63 #cooling-cells = <2>;72 #cooling-cells = <2>;81 #cooling-cells = <2>;[all...]
18 #address-cells = <2>;19 #size-cells = <2>;39 #cooling-cells = <2>;56 #cooling-cells = <2>;61 cache-level = <2>;124 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |141 #address-cells = <2>;[all...]
19 #address-cells = <2>;20 #size-cells = <2>;39 /* DRAM space - 1, size : 2 GB DRAM */57 #address-cells = <2>;58 #size-cells = <2>;100 thermal-sensors = <&tmu 2>;262 #address-cells = <2>;263 #size-cells = <2>;270 #clock-cells = <2>;298 #interrupt-cells = <2>;[all...]
18 #address-cells = <2>;19 #size-cells = <2>;30 #address-cells = <2>;31 #size-cells = <2>;136 #address-cells = <2>;149 cache-level = <2>;164 CPU2: cpu@2 {194 cache-level = <2>;433 qcom,remote-pid = <2>;444 #interrupt-cells = <2>;[all...]