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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm632.dtsi44 * SDM632 uses Kryo 250 instead of Cortex A53
65 capacity-dmips-mhz = <1980>;
70 capacity-dmips-mhz = <1980>;
75 capacity-dmips-mhz = <1980>;
80 capacity-dmips-mhz = <1980>;
H A Dmsm8976.dtsi41 capacity-dmips-mhz = <573>;
52 capacity-dmips-mhz = <573>;
63 capacity-dmips-mhz = <573>;
74 capacity-dmips-mhz = <573>;
85 capacity-dmips-mhz = <1024>;
96 capacity-dmips-mhz = <1024>;
107 capacity-dmips-mhz = <1024>;
118 capacity-dmips-mhz = <1024>;
1703 polling-delay-passive = <250>;
1717 polling-delay-passive = <250>;
[all …]
H A Dmsm8998.dtsi145 capacity-dmips-mhz = <1024>;
160 capacity-dmips-mhz = <1024>;
170 capacity-dmips-mhz = <1024>;
180 capacity-dmips-mhz = <1024>;
190 capacity-dmips-mhz = <1536>;
205 capacity-dmips-mhz = <1536>;
215 capacity-dmips-mhz = <1536>;
225 capacity-dmips-mhz = <1536>;
491 polling-delay-passive = <250>;
511 polling-delay-passive = <250>;
[all …]
H A Dmsm8953.dtsi49 capacity-dmips-mhz = <1024>;
61 capacity-dmips-mhz = <1024>;
73 capacity-dmips-mhz = <1024>;
85 capacity-dmips-mhz = <1024>;
97 capacity-dmips-mhz = <1024>;
109 capacity-dmips-mhz = <1024>;
121 capacity-dmips-mhz = <1024>;
133 capacity-dmips-mhz = <1024>;
1201 * sdm632, the max for sdm450 is 600MHz.
2103 polling-delay-passive = <250>;
[all …]
H A Dsdm630.dtsi63 capacity-dmips-mhz = <1126>;
83 capacity-dmips-mhz = <1126>;
98 capacity-dmips-mhz = <1126>;
113 capacity-dmips-mhz = <1126>;
128 capacity-dmips-mhz = <1024>;
148 capacity-dmips-mhz = <1024>;
163 capacity-dmips-mhz = <1024>;
178 capacity-dmips-mhz = <1024>;
2247 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2463 polling-delay-passive = <250>;
[all …]
H A Dsc8180x.dtsi52 capacity-dmips-mhz = <602>;
81 capacity-dmips-mhz = <602>;
106 capacity-dmips-mhz = <602>;
130 capacity-dmips-mhz = <602>;
154 capacity-dmips-mhz = <1024>;
178 capacity-dmips-mhz = <1024>;
202 capacity-dmips-mhz = <1024>;
226 capacity-dmips-mhz = <1024>;
3942 polling-delay-passive = <250>;
3956 polling-delay-passive = <250>;
[all …]
H A Dsc7180.dtsi89 capacity-dmips-mhz = <415>;
118 capacity-dmips-mhz = <415>;
142 capacity-dmips-mhz = <415>;
166 capacity-dmips-mhz = <415>;
190 capacity-dmips-mhz = <415>;
214 capacity-dmips-mhz = <415>;
238 capacity-dmips-mhz = <1024>;
262 capacity-dmips-mhz = <1024>;
4041 polling-delay-passive = <250>;
4089 polling-delay-passive = <250>;
[all …]
H A Dsm8150.dtsi58 capacity-dmips-mhz = <488>;
87 capacity-dmips-mhz = <488>;
111 capacity-dmips-mhz = <488>;
135 capacity-dmips-mhz = <488>;
159 capacity-dmips-mhz = <1024>;
183 capacity-dmips-mhz = <1024>;
207 capacity-dmips-mhz = <1024>;
231 capacity-dmips-mhz = <1024>;
927 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
4614 polling-delay-passive = <250>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dbrcm,iproc-clocks.yaml119 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
227 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
339 - const: 250mhz
394 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
H A Dbrcm,iproc-clocks.txt44 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
113 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
210 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
106 exit-latency-us = <250>;
128 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
106 exit-latency-us = <250>;
128 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatop.c119 * 396MHz, it also says that the ARM and SOC voltages can't differ by
124 uint32_t mhz; member
136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
266 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); in cpufreq_nearest_oppt()
281 if (op->mhz > sc->cpu_curmhz) { in cpufreq_set_clock()
289 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. in cpufreq_set_clock()
294 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv); in cpufreq_set_clock()
316 if (op->mhz < sc->cpu_curmhz) in cpufreq_set_clock()
318 sc->cpu_curmhz = op->mhz; in cpufreq_set_clock()
341 if (op->mhz > sc->cpu_maxmhz) in cpufreq_sysctl_minmhz()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dthermal-cooling-devices.yaml72 capacity-dmips-mhz = <607>;
98 polling-delay-passive = <250>;
114 /* Corresponds to 1000MHz in OPP table */
H A Dthermal-zones.yaml278 polling-delay-passive = <250>;
306 /* Corresponds to 1400MHz in OPP table */
313 /* Corresponds to 1000MHz in OPP table */
323 polling-delay-passive = <250>;
345 polling-delay-passive = <250>;
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8192.dtsi76 capacity-dmips-mhz = <427>;
95 capacity-dmips-mhz = <427>;
114 capacity-dmips-mhz = <427>;
133 capacity-dmips-mhz = <427>;
152 capacity-dmips-mhz = <1024>;
171 capacity-dmips-mhz = <1024>;
190 capacity-dmips-mhz = <1024>;
209 capacity-dmips-mhz = <1024>;
1959 polling-delay-passive = <250>;
1989 polling-delay-passive = <250>;
[all …]
H A Dmt8183.dtsi332 capacity-dmips-mhz = <741>;
355 capacity-dmips-mhz = <741>;
378 capacity-dmips-mhz = <741>;
401 capacity-dmips-mhz = <741>;
424 capacity-dmips-mhz = <1024>;
447 capacity-dmips-mhz = <1024>;
470 capacity-dmips-mhz = <1024>;
493 capacity-dmips-mhz = <1024>;
527 entry-latency-us = <250>;
535 entry-latency-us = <250>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
397 0: 16 MHz (4 MHz)
398 1: 8 MHz (2 MHz)
399 2: 4 MHz (1 MHz)
400 3: 2 MHz (500 kHz)
603 0: 4 MHz (1 MHz)
604 1: 2 MHz (500 kHz)
605 2: 1 MHz (250 kHz)
H A Diqs269a.yaml180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (500 kHz)
389 0: 4 MHz (1 MHz)
390 1: 2 MHz (50
[all...]
/freebsd/sys/net80211/
H A Dieee80211_regdomain.h110 CTRY_FRANCE = 250, /* France */
258 SKU_SR9 = 0x0298, /* Ubiquiti SR9 (900MHz/GSM) */
259 SKU_XR9 = 0x0299, /* Ubiquiti XR9 (900MHz/GSM) */
260 SKU_GZ901 = 0x029a, /* Zcomax GZ-901 (900MHz/GSM) */
261 SKU_XC900M = 0x029b, /* Xagyl XC900M (900MHz/GSM) */
266 * offset channel spacing (905MHz-
267 * 925MHz) versus the XR9 (907MHz-
268 * 922MHz), giving an extra channel.
/freebsd/sys/arm/mv/armada38x/
H A Darmada38x.c66 * On Armada38x TCLK can be configured to 250 MHz or 200 MHz. in get_tclk_armada38x()
/freebsd/sys/contrib/device-tree/src/arm64/exynos/google/
H A Dgs101.dtsi77 capacity-dmips-mhz = <250>;
87 capacity-dmips-mhz = <250>;
97 capacity-dmips-mhz = <250>;
107 capacity-dmips-mhz = <250>;
117 capacity-dmips-mhz = <620>;
127 capacity-dmips-mhz = <620>;
137 capacity-dmips-mhz = <1024>;
147 capacity-dmips-mhz = <1024>;
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-cygnus-clock.dtsi75 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
/freebsd/sys/contrib/device-tree/src/mips/mobileye/
H A Deyeq5-clocks.dtsi263 clock-frequency = <250000000>; /* 250MHz */
268 clock-frequency = <125000000>; /* 125MHz */
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-emcon.dtsi41 128 144 160 176 250
294 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
309 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
343 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
355 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {

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