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/linux/include/video/
H A Dsh_mobile_lcdc.h50 #define LDMT1R_DAPOL (1 << 24)
95 #define LDDWDxR_RSW (1 << 24)
97 #define LDDRDR_RSR (1 << 24)
105 RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */
106 RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */
107 RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */
108 RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */
109 RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */
110 RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */
111 RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */
[all …]
/linux/drivers/gpu/drm/renesas/shmobile/
H A Dshmob_drm_kms.c31 .bpp = 16,
38 .bpp = 24,
45 .bpp = 32,
52 .bpp = 32,
59 .bpp = 12,
66 .bpp = 12,
73 .bpp = 16,
80 .bpp = 16,
87 .bpp = 24,
94 .bpp = 24,
[all …]
/linux/drivers/video/fbdev/matrox/
H A Dmatroxfb_DAC1064.h67 #define M1064_XMULCTRL_DEPTH_8BPP 0x00 /* 8 bpp paletized */
68 #define M1064_XMULCTRL_DEPTH_15BPP_1BPP 0x01 /* 15 bpp paletized + 1 bpp overlay */
69 #define M1064_XMULCTRL_DEPTH_16BPP 0x02 /* 16 bpp paletized */
70 #define M1064_XMULCTRL_DEPTH_24BPP 0x03 /* 24 bpp paletized */
71 #define M1064_XMULCTRL_DEPTH_24BPP_8BPP 0x04 /* 24 bpp direct + 8 bpp overlay paletized */
72 #define M1064_XMULCTRL_2G8V16 0x05 /* 15 bpp video direct, half xres, 8bpp paletized */
73 #define M1064_XMULCTRL_G16V16 0x06 /* 15 bpp video, 15bpp graphics, one of them paletized */
74 #define M1064_XMULCTRL_DEPTH_32BPP 0x07 /* 24 bpp paletized + 8 bpp unused */
/linux/Documentation/fb/
H A Dmatroxfb.rst43 bpp 640x400 640x480 768x576 800x600 960x720
49 24 0x1B2 0x184 0x1B5 0x18C
58 bpp 1024x768 1152x864 1280x1024 1408x1056 1600x1200
64 24 0x1B8 0x194 0x1BB 0x19C 0x1BF
91 architectures there are some glitches for 24bpp videomodes. 8, 16 and 32bpp
194 inv24 change timings parameters for 24bpp modes on Millennium and
216 4bpp, 8bpp). In DIRECTCOLOR modes it is limited to characters
249 has 8bpp support. Otherwise first available of 640x350x4bpp,
282 depth:X Bits per pixel: 0=text, 4,8,15,16,24 or 32. Default depends on
313 - 24bpp does not support correctly XF-FBDev on big-endian architectures.
[all …]
H A Ds3fb.rst26 * 4 bpp pseudocolor modes (with 18bit palette, two variants)
27 * 8 bpp pseudocolor mode (with 18bit palette)
28 * 16 bpp truecolor modes (RGB 555 and RGB 565)
29 * 24 bpp truecolor mode (RGB 888) on (only on Virge VX)
30 * 32 bpp truecolor mode (RGB 888) on (not on Virge VX)
31 * text mode (activated by bpp = 0)
45 There are two 4 bpp modes. First mode (selected if nonstd == 0) is mode with
62 * 24 bpp mode support on more cards
63 * support for fontwidths != 8 in 4 bpp modes
H A Dpxafb.rst21 mode:XRESxYRES[-BPP]
29 BPP == The bit depth. Valid values are 1, 2, 4, 8 and 16.
104 var->xres_virtual * var->yres_virtual * bpp
106 bpp = 16 -- for RGB565 or RGBT555
108 bpp = 24 -- for YUV444 packed
110 bpp = 24 -- for YUV444 planar
112 bpp = 16 -- for YUV422 planar (1 pixel = 1 Y + 1/2 Cb + 1/2 Cr)
114 bpp = 12 -- for YUV420 planar (1 pixel = 1 Y + 1/4 Cb + 1/4 Cr)
H A Darkfb.rst19 * 4 bpp pseudocolor modes (with 18bit palette, two variants)
20 * 8 bpp pseudocolor mode (with 18bit palette)
21 * 16 bpp truecolor modes (RGB 555 and RGB 565)
22 * 24 bpp truecolor mode (RGB 888)
23 * 32 bpp truecolor mode (RGB 888)
24 * text mode (activated by bpp = 0)
36 There are two 4 bpp modes. First mode (selected if nonstd == 0) is mode with
54 * support for fontwidths != 8 in 4 bpp modes
H A Dintel810.rst37 - Supports color depths of 8, 16, 24 and 32 bits per pixel
41 - Full and optimized hardware acceleration at 8, 16 and 24 bpp
93 f. "bpp:<value>"
168 than 8 bpp. Useful for color tuning, such as gamma control.
173 o. <xres>x<yres>[-<bpp>][@<refresh>]
191 append="video=i810fb:vram:2,xres:1024,yres:768,bpp:8,hsync1:30,hsync2:55, \
194 This will initialize the framebuffer to 1024x768 at 8bpp. The framebuffer
219 modprobe i810fb vram=2 xres=1024 bpp=8 hsync1=30 hsync2=55 vsync1=50 \
224 options i810fb vram=2 xres=1024 bpp=16 hsync1=30 hsync2=55 vsync1=50 \
H A Dpvr2fb.rst33 mode:X default video mode with format [xres]x[yres]-<bpp>@<refresh rate>
35 640x640-16@60, 640x480-24@60, 640x480-32@60. The Dreamcast
37 24bpp and 32bpp modes function poorly. Work to fix that is
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_kms.c45 .bpp = 16,
53 .bpp = 16,
61 .bpp = 16,
68 .bpp = 32,
76 .bpp = 32,
84 .bpp = 16,
92 .bpp = 16,
100 .bpp = 12,
108 .bpp = 12,
116 .bpp = 16,
[all …]
/linux/drivers/video/fbdev/aty/
H A Dmach64_accel.c76 if (info->var.bits_per_pixel == 24) { in aty_init_engine()
77 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ in aty_init_engine()
214 if (info->var.bits_per_pixel == 24) { in atyfb_copyarea()
215 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ in atyfb_copyarea()
234 if (info->var.bits_per_pixel == 24) { in atyfb_copyarea()
267 if (info->var.bits_per_pixel == 24) { in atyfb_fillrect()
268 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ in atyfb_fillrect()
326 case 24: in atyfb_imageblit()
336 if (info->var.bits_per_pixel == 24) { in atyfb_imageblit()
337 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ in atyfb_imageblit()
[all …]
H A Dmach64_gx.c81 const union aty_pll *pll, u32 bpp, u32 accel) in aty_set_dac_514() argument
92 0, 0x41, 0x03, 0x71, 0x45}, /* 8 bpp */ in aty_set_dac_514()
100 switch (bpp) { in aty_set_dac_514()
119 /* Misc Control 2 / 16 BPP Control / 32 BPP Control */ in aty_set_dac_514()
124 u32 bpp, union aty_pll *pll) in aty_var_to_pll_514() argument
206 const union aty_pll *pll, u32 bpp, in aty_set_dac_ATI68860_B() argument
215 switch (bpp) { in aty_set_dac_ATI68860_B()
229 case 24: in aty_set_dac_ATI68860_B()
289 const union aty_pll *pll, u32 bpp, in aty_set_dac_ATT21C498() argument
299 switch (bpp) { in aty_set_dac_ATT21C498()
[all …]
/linux/drivers/gpu/drm/tests/
H A Ddrm_cmdline_parser_test.c204 const char *cmdline = "720x480-24"; in drm_test_cmdline_res_bpp()
215 KUNIT_EXPECT_EQ(test, mode.bpp, 24); in drm_test_cmdline_res_bpp()
250 const char *cmdline = "720x480-24@60"; in drm_test_cmdline_res_bpp_refresh()
262 KUNIT_EXPECT_EQ(test, mode.bpp, 24); in drm_test_cmdline_res_bpp_refresh()
274 const char *cmdline = "720x480-24@60i"; in drm_test_cmdline_res_bpp_refresh_interlaced()
286 KUNIT_EXPECT_EQ(test, mode.bpp, 24); in drm_test_cmdline_res_bpp_refresh_interlaced()
298 const char *cmdline = "720x480-24@60m"; in drm_test_cmdline_res_bpp_refresh_margins()
310 KUNIT_EXPECT_EQ(test, mode.bpp, 24); in drm_test_cmdline_res_bpp_refresh_margins()
322 const char *cmdline = "720x480-24@60d"; in drm_test_cmdline_res_bpp_refresh_force_off()
334 KUNIT_EXPECT_EQ(test, mode.bpp, 24); in drm_test_cmdline_res_bpp_refresh_force_off()
[all …]
H A Ddrm_dp_mst_helper_test.c17 const int bpp; member
25 .bpp = 30,
31 .bpp = 30,
37 .bpp = 24,
43 .bpp = 24,
49 .bpp = 24,
59 KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp << 4), in drm_test_dp_mst_calc_pbn_mode()
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
/linux/drivers/video/fbdev/
H A Dtridentfb.c65 static int bpp = 8; variable
83 module_param(bpp, int, 0);
305 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) in blade_init_accel() argument
308 int tmp = bpp == 24 ? 2 : (bpp >> 4); in blade_init_accel()
379 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp) in xp_init_accel() argument
381 unsigned char x = bpp == 24 ? 3 : (bpp >> 4); in xp_init_accel()
382 int v1 = pitch << (bpp == 24 ? 20 : (18 + x)); in xp_init_accel()
384 switch (pitch << (bpp >> 3)) { in xp_init_accel()
477 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp) in image_init_accel() argument
479 int tmp = bpp == 24 ? 2: (bpp >> 4); in image_init_accel()
[all …]
H A Di740fb.c209 static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp) in i740_calc_fifo() argument
221 switch (bpp) { in i740_calc_fifo()
270 case 24: in i740_calc_fifo()
403 u32 bpp, base, dacspeed24, mem, freq; in i740fb_decode_var() local
409 dev_dbg(info->device, " xoff: %i, yoff: %i, bpp: %i, graysc: %i\n", in i740fb_decode_var()
421 bpp = var->bits_per_pixel; in i740fb_decode_var()
422 switch (bpp) { in i740fb_decode_var()
424 bpp = 8; in i740fb_decode_var()
426 dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n", in i740fb_decode_var()
432 bpp = 15; in i740fb_decode_var()
[all …]
H A Dpxafb.c242 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
249 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
252 int bpp = -EINVAL; in pxafb_var_to_bpp() local
255 case 1: bpp = 0; break; in pxafb_var_to_bpp()
256 case 2: bpp = 1; break; in pxafb_var_to_bpp()
257 case 4: bpp = 2; break; in pxafb_var_to_bpp()
258 case 8: bpp = 3; break; in pxafb_var_to_bpp()
259 case 16: bpp = 4; break; in pxafb_var_to_bpp()
260 case 24: in pxafb_var_to_bpp()
262 case 18: bpp = 6; break; /* 18-bits/pixel packed */ in pxafb_var_to_bpp()
[all …]
H A Dsunxvr500.c87 #define RAMDAC_VID_32FB_0 0x00000078UL /* PCI base 32bpp FB buffer 0 */
88 #define RAMDAC_VID_32FB_1 0x0000007cUL /* PCI base 32bpp FB buffer 1 */
89 #define RAMDAC_VID_8FB_0 0x00000080UL /* PCI base 8bpp FB buffer 0 */
90 #define RAMDAC_VID_8FB_1 0x00000084UL /* PCI base 8bpp FB buffer 1 */
128 value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8); in e3d_setcolreg()
145 * XXX two 8bpp areas of the framebuffer work. I imagine there is
147 * XXX the ramdac which of the two 8bpp framebuffer regions to take
216 if (ep->depth == 32 || ep->depth == 24) in e3d_set_fbinfo()
231 var->blue.offset = 24; in e3d_set_fbinfo()
344 case 24: in e3d_pci_register()
H A Ds3c-fb.c116 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
118 * valid_bpp bit x is set if (x+1)BPP is supported.
225 * @bpp: The bit depth.
227 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp) in s3c_fb_validate_win_bpp() argument
229 return win->variant.valid_bpp & VALID_BPP(bpp); in s3c_fb_validate_win_bpp()
252 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n", in s3c_fb_check_var()
302 /* 16 bpp, 565 format */ in s3c_fb_check_var()
314 var->transp.length = var->bits_per_pixel - 24; in s3c_fb_check_var()
315 var->transp.offset = 24; in s3c_fb_check_var()
317 case 24: in s3c_fb_check_var()
[all …]
/linux/arch/arm/mach-s3c/
H A Dfb.h25 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
27 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
/linux/drivers/gpu/drm/gma500/
H A Doaktrail.h89 /* Bit0: 16bpp (not supported in LNC), */
90 /* Bit1: 18bpp loosely packed, */
91 /* Bit2: 18bpp packed, */
92 /* Bit3: 24bpp */
119 /* Bit0: 16bpp (not supported in LNC), */
120 /* Bit1: 18bpp loosely packed, */
121 /* Bit2: 18bpp packed, */
122 /* Bit3: 24bpp */
/linux/drivers/video/fbdev/core/
H A Dfb_fillrect.h20 * reverse pixel order in a byte (<8 BPP), word length of 32/64 bits,
69 static unsigned long pixel_to_pat(int bpp, u32 color) in pixel_to_pat() argument
81 switch (bpp) { in pixel_to_pat()
83 pattern = mulconst[bpp] * color; in pixel_to_pat()
87 pattern = pattern | pattern << bpp; in pixel_to_pat()
88 pattern = pattern | pattern << bpp*2; in pixel_to_pat()
92 pattern = pattern | pattern << bpp; in pixel_to_pat()
98 pattern <<= (BITS_PER_LONG % bpp); in pixel_to_pat()
99 pattern |= pattern >> bpp; in pixel_to_pat()
201 /* pattern doesn't change. 1, 2, 4, 8, 16, 32, 64 bpp */
[all …]
/linux/drivers/staging/sm750fb/
H A Dsm750_accel.h50 #define DE_CONTROL_STEP_Y BIT(24)
86 #define DE_CONTROL_SHORT_STROKE_DIR_MASK (0xf << 24)
87 #define DE_CONTROL_SHORT_STROKE_DIR_225 (0x0 << 24)
88 #define DE_CONTROL_SHORT_STROKE_DIR_135 (0x1 << 24)
89 #define DE_CONTROL_SHORT_STROKE_DIR_315 (0x2 << 24)
90 #define DE_CONTROL_SHORT_STROKE_DIR_45 (0x3 << 24)
91 #define DE_CONTROL_SHORT_STROKE_DIR_270 (0x4 << 24)
92 #define DE_CONTROL_SHORT_STROKE_DIR_90 (0x5 << 24)
93 #define DE_CONTROL_SHORT_STROKE_DIR_180 (0x8 << 24)
94 #define DE_CONTROL_SHORT_STROKE_DIR_0 (0xa << 24)
[all …]
/linux/drivers/staging/media/imx/
H A Dimx-media-utils.c24 .bpp = 16,
32 .bpp = 16,
36 .bpp = 12,
41 .bpp = 12,
46 .bpp = 16,
51 .bpp = 12,
56 .bpp = 16,
62 .bpp = 32,
70 .bpp = 16,
79 .bpp = 24,
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dcik_reg.h52 /* 8 BPP */
54 /* 16 BPP */
61 /* 32 BPP */
93 # define CIK_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
122 # define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
140 # define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
175 #define SDMA_RB_VMID(x) (x << 24)
230 uint32_t mask:24;

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