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/linux/drivers/video/logo/
H A Dlogo_parisc_clut224.ppm5 2 2 2 2 2 2 2 2 2 2 2 2
6 2 2 2 2 2 2 2 2 2 2 2 2
7 2 2 2 2 2 2 2 2 2 2 2 2
8 2 2 2 2 2 2 2 2 2 2 2 2
9 2 2 2 2 2 2 2 2 2 2 2 2
10 2 2 2 2 2 2 2 2 2 2 2 2
11 2 2 2 2 2 2 2 2 2 2 2 2
12 2 2 2 2 2 2 2 2 2 2 2 2
13 2 2 2 2 2 2 2 2 2 2 2 2
14 2 2 2 2 2 2 6 6 7 6 6 7
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H A Dlogo_superh_clut224.ppm5 2 2 2 2 2 2 2 2 2 2 2 2
6 2 2 2 2 2 2 2 2 2 2 2 2
7 2 2 2 2 2 2 2 2 2 2 2 2
8 2 2 2 2 2 2 2 2 2 2 2 2
9 2 2 2 2 2 2 2 2 2 2 2 2
10 2 2 2 2 2 2 2 2 2 2 2 2
11 2 2 2 2 2 2 2 2 2 2 2 2
12 2 2 2 2 2 2 2 2 2 2 2 2
13 2 2 2 2 2 2 2 2 2 2 2 2
16 2 2 2 2 2 2 2 2 2 2 2 2
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H A Dlogo_linux_clut224.ppm94 2 2 6 2 2 6 2 2 6 2 2 6
95 2 2 6 2 2 6 2 2 6 2 2 6
113 78 78 78 34 34 34 2 2 6 2 2 6
114 2 2 6 2 2 6 2 2 6 2 2 6
115 2 2 6 2 2 6 2 2 6 2 2 6
116 2 2 6 2 2 6 6 6 6 70 70 70
133 26 26 26 2 2 6 2 2 6 2 2 6
134 2 2 6 2 2 6 2 2 6 2 2 6
135 2 2 6 2 2 6 2 2 6 14 14 14
136 46 46 46 34 34 34 6 6 6 2 2 6
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H A Dlogo_sun_clut224.ppm94 2 2 6 2 2 6 2 2 6 2 2 6
95 2 2 6 2 2 6 2 2 6 2 2 6
113 78 78 78 34 34 34 2 2 6 2 2 6
114 2 2 6 2 2 6 2 2 6 2 2 6
115 2 2 6 2 2 6 2 2 6 2 2 6
116 2 2 6 2 2 6 6 6 6 70 70 70
133 26 26 26 2 2 6 2 2 6 2 2 6
134 2 2 6 2 2 6 2 2 6 2 2 6
135 2 2 6 2 2 6 2 2 6 14 14 14
136 46 46 46 34 34 34 6 6 6 2 2 6
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H A Dlogo_sgi_clut224.ppm94 2 2 6 2 2 6 2 2 6 2 2 6
95 2 2 6 2 2 6 2 2 6 2 2 6
113 78 78 78 34 34 34 2 2 6 2 2 6
114 2 2 6 2 2 6 2 2 6 2 2 6
115 2 2 6 2 2 6 2 2 6 2 2 6
116 2 2 6 2 2 6 6 6 6 70 70 70
133 26 26 26 2 2 6 2 2 6 2 2 6
134 2 2 6 2 2 6 2 2 6 2 2 6
135 2 2 6 2 2 6 2 2 6 14 14 14
136 46 46 46 34 34 34 6 6 6 2 2 6
[all …]
H A Dlogo_dec_clut224.ppm94 2 2 6 2 2 6 2 2 6 2 2 6
95 2 2 6 2 2 6 2 2 6 2 2 6
113 78 78 78 34 34 34 2 2 6 2 2 6
114 2 2 6 2 2 6 2 2 6 2 2 6
115 2 2 6 2 2 6 2 2 6 2 2 6
116 2 2 6 2 2 6 6 6 6 70 70 70
133 26 26 26 2 2 6 2 2 6 2 2 6
134 2 2 6 2 2 6 2 2 6 2 2 6
135 2 2 6 2 2 6 2 2 6 14 14 14
136 46 46 46 34 34 34 6 6 6 2 2 6
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h41 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
43 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
45 …ne mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
47 …ne mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
49 …ne mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
51 …ne mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
53 …ne mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
55 …ne mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
57 …ne mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
63 …ne mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h163 …ne mmRBBMIF_TIMEOUT_BASE_IDX 2
165 …ne mmRBBMIF_STATUS_BASE_IDX 2
167 …ne mmRBBMIF_STATUS_2_BASE_IDX 2
169 …ne mmRBBMIF_INT_STATUS_BASE_IDX 2
171 …ne mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
173 …ne mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2
175 …ne mmRBBMIF_STATUS_FLAG_BASE_IDX 2
180 …ne mmAZ_CLOCK_CNTL_BASE_IDX 2
186 …ne mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
188 …ne mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
[all …]
H A Ddcn_2_0_0_offset.h333 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
335 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
337 …ne mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
339 …ne mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
341 …ne mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
343 …ne mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
345 …ne mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
347 …ne mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
349 …ne mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
355 …ne mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
[all …]
H A Ddcn_2_1_0_offset.h323 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
325 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
327 …ne mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
329 …ne mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
331 …ne mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
333 …ne mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
335 …ne mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
337 …ne mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
339 …ne mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
345 …ne mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
[all …]
H A Ddcn_1_0_offset.h681 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
683 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
685 …ne mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
687 …ne mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
689 …ne mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
691 …ne mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
693 …ne mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
695 …ne mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
697 …ne mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
703 …ne mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
[all …]
H A Ddcn_4_1_0_offset.h229 …e regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2
231 …e regHDMICHARCLK1_CLOCK_CNTL_BASE_IDX 2
233 …e regHDMICHARCLK2_CLOCK_CNTL_BASE_IDX 2
235 …e regHDMICHARCLK3_CLOCK_CNTL_BASE_IDX 2
237 …e regHDMICHARCLK4_CLOCK_CNTL_BASE_IDX 2
239 …e regHDMICHARCLK5_CLOCK_CNTL_BASE_IDX 2
241 …e regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2
243 …e regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2
245 …e regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2
247 …e regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2
[all …]
H A Ddcn_3_0_1_offset.h355 …ne mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2
357 …ne mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2
359 …ne mmPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2
361 …ne mmPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2
373 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
375 …ne mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
377 …ne mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
379 …ne mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
381 …ne mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
383 …ne mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
[all …]
H A Ddcn_3_5_1_offset.h1342 …e regDTBCLK_DTO0_PHASE_BASE_IDX 2
1344 …e regDTBCLK_DTO1_PHASE_BASE_IDX 2
1346 …e regDTBCLK_DTO2_PHASE_BASE_IDX 2
1348 …e regDTBCLK_DTO3_PHASE_BASE_IDX 2
1350 …e regDTBCLK_DTO0_MODULO_BASE_IDX 2
1352 …e regDTBCLK_DTO1_MODULO_BASE_IDX 2
1354 …e regDTBCLK_DTO2_MODULO_BASE_IDX 2
1356 …e regDTBCLK_DTO3_MODULO_BASE_IDX 2
1358 …e regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2
1360 …e regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2
[all …]
H A Ddcn_3_5_0_offset.h1363 …e regDTBCLK_DTO0_PHASE_BASE_IDX 2
1365 …e regDTBCLK_DTO1_PHASE_BASE_IDX 2
1367 …e regDTBCLK_DTO2_PHASE_BASE_IDX 2
1369 …e regDTBCLK_DTO3_PHASE_BASE_IDX 2
1371 …e regDTBCLK_DTO0_MODULO_BASE_IDX 2
1373 …e regDTBCLK_DTO1_MODULO_BASE_IDX 2
1375 …e regDTBCLK_DTO2_MODULO_BASE_IDX 2
1377 …e regDTBCLK_DTO3_MODULO_BASE_IDX 2
1379 …e regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2
1381 …e regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_0_0_offset.h16 …ne mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
18 …ne mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
20 …ne mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
22 …ne mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
24 …ne mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
26 …ne mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
28 …ne mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
34 …ne mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
36 …ne mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
38 …ne mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
[all …]
H A Ddpcs_2_1_0_offset.h29 …ne mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
31 …ne mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
33 …ne mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
35 …ne mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
37 …ne mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
39 …ne mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
41 …ne mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
47 …ne mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
49 …ne mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
51 …ne mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
[all …]
H A Ddpcs_2_0_0_offset.h29 …ne mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
31 …ne mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
33 …ne mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
35 …ne mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
37 …ne mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
39 …ne mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
41 …ne mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
47 …ne mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
49 …ne mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
51 …ne mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
[all …]
H A Ddpcs_3_0_3_offset.h16 …ne mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
18 …ne mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
20 …ne mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
22 …ne mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
24 …ne mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
26 …ne mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
32 …ne mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
34 …ne mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
36 …ne mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
38 …ne mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
[all …]
/linux/arch/powerpc/lib/
H A Dfeature-fixups-test.S20 or 2,2,2 /* fixup will nop out this instruction */
27 or 2,2,2
37 or 2,2,2 /* fixup will replace this with ftr_fixup_test2_alt */
44 or 2,2,2
57 or 2,2,2 /* fixup will fail to replace this */
64 or 2,2,2
73 or 2,2,2
74 or 2,2,2
75 or 2,2,2
76 or 2,2,2
[all …]
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_security.c514 word_offset = ((mmMME0_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; in gaudi_init_mme_protection_bits()
515 mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
516 mask |= 1U << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
517 mask |= 1U << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
518 mask |= 1U << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
519 mask |= 1U << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
520 mask |= 1U << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
521 mask |= 1U << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
522 mask |= 1U << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
523 mask |= 1U << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
[all …]
/linux/drivers/accel/habanalabs/goya/
H A Dgoya_security.c68 word_offset = ((mmMME_DUMMY & PROT_BITS_OFFS) >> 7) << 2; in goya_init_mme_protection_bits()
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
74 mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2); in goya_init_mme_protection_bits()
75 mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2); in goya_init_mme_protection_bits()
76 mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2); in goya_init_mme_protection_bits()
77 mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
/linux/arch/xtensa/variants/de212/include/variant/
H A Dtie.h58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
62 * galign = group byte alignment (power of 2) (galign >= align)
63 * align = register byte alignment (power of 2)
123 #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
126 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
127 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
128 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
129 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
130 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
[all …]
/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dtaprio.json15 …: "$TC qdisc add dev $ETH root handle 1: taprio num_tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queue…
18 … "matchPattern": "qdisc taprio 1: root refcnt [0-9]+ tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2",
37 …: "$TC qdisc add dev $ETH root handle 1: taprio num_tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queue…
59 …: "$TC qdisc add dev $ETH root handle 1: taprio num_tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queue…
80 …"$TC qdisc add dev $ETH root handle 1: taprio num_tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queues …
104 …: "$TC qdisc add dev $ETH root handle 1: taprio num_tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queue…
126 …: "$TC qdisc add dev $ETH root handle 1: taprio num_tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queue…
127 "expExitCode": "2",
148 …"cmdUnderTest": "$TC qdisc add dev $ETH root handle 1: taprio num_tc 2 queues 1@0 1@1 sched-entry …
149 "expExitCode": "2",
[all …]
/linux/drivers/media/platform/verisilicon/
H A Dhantro_vp9.h10 u8 sign[2];
11 u8 class0_bit[2][1];
12 u8 fr[2][3];
13 u8 class0_hp[2];
14 u8 hp[2];
15 u8 classes[2][10];
16 u8 class0_fr[2][2][3];
17 u8 bits[2][10];
24 u8 tx8[2][1];
25 u8 tx16[2][2];
[all …]

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