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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PerfectShuffle.h1 //===-- AArch64PerfectShuffle.h - AdvSIMD Perfect Shuffle Table -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file, which was autogenerated by llvm-PerfectShuffle, contains data
12 //===----------------------------------------------------------------------===//
23 // 3690 entries have cost 2
29 2080972802U, // <0,0,0,1>: Cost 2 ins <0,0,u,1>, lane 2
30 1679065190U, // <0,0,0,2>: Cost 2 vuzpl <0,2,0,2>, LHS
31 2085707777U, // <0,0,0,3>: Cost 2 ins <0,u,0,3>, lane 1
32 1476398390U, // <0,0,0,4>: Cost 2 vext1 <0,0,0,0>, RHS
[all …]
/freebsd/sys/arm64/rockchip/
H A Drk_typec_phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
11 * 2. Redistributions in binary form must reproduce the above copyright
66 #define CMN_PLL0_VCOCAL_INIT (0x84 << 2)
67 #define CMN_PLL0_VCOCAL_ITER (0x85 << 2)
68 #define CMN_PLL0_INTDIV (0x94 << 2)
69 #define CMN_PLL0_FRACDIV (0x95 << 2)
70 #define CMN_PLL0_HIGH_THR (0x96 << 2)
71 #define CMN_PLL0_DSM_DIAG (0x97 << 2)
72 #define CMN_PLL0_SS_CTRL1 (0x98 << 2)
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
20 vcc-supply:
23 enable-gpios: true
24 orientation-switch: true
25 retimer-switch: true
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/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_kr.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
38 * Ethernet KR auto-neg and link-training driver API
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
59 /* AN (Auto-negotiation) Advertisement Registers */
83 #define AL_ETH_AN_TECH_10GBASE_KR AL_BIT(2)
103 /* Acknowledge 2 is used to indicate that the receiver is able to act on the information
117 C72_CSTATE_MIN = 2,
124 AL_PHY_KR_COEF_UP_DEC = 2,
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H A Dal_hal_eth_kr.c1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
41 * @brief KR HAL driver for main functions (auto-neg, Link Training)
130 /* register 2 */
165 #define AL_ETH_KR_PMD_STATUS_RECEIVER_START_UP_PROTO_PROG_SHIFT 2
171 #define AL_ETH_KR_PMD_LP_COEF_UP_ZERO_SHIFT 2
180 #define AL_ETH_KR_PMD_LP_STATUS_REPORT_ZERO_SHIFT 2
188 #define AL_ETH_KR_PMD_LD_COEF_UP_ZERO_SHIFT 2
197 #define AL_ETH_KR_PMD_LD_STATUS_REPORT_ZERO_SHIFT 2
212 enum al_eth_an_lt_lane lane) in al_eth_an_lt_reg_read() argument
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H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
58 uint32_t reserved1[2];
365 uint32_t phy_id[2];
387 uint32_t rsrvd_0[2];
416 /* [0x44] MDIO control register for MDIO interface 2 */
418 /* [0x48] MDIO information register for MDIO interface 2 */
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
621 * [0x84] SERDES 32-bit interface bit selection
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_25g.c9 found at http://www.gnu.org/licenses/gpl-2.0.html
73 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base; in al_serdes_25g_reg_read()
94 return -1; in al_serdes_25g_reg_read()
97 al_reg_write32(&regs_base->gen.reg_addr, addr); in al_serdes_25g_reg_read()
98 *data = al_reg_read32(&regs_base->gen.reg_data); in al_serdes_25g_reg_read()
112 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base; in al_serdes_25g_reg_write()
132 return -1; in al_serdes_25g_reg_write()
135 al_reg_write32(&regs_base->gen.reg_addr, addr); in al_serdes_25g_reg_write()
136 al_reg_write32(&regs_base->gen.reg_data, (data | SERDES_C_GEN_REG_DATA_STRB_MASK)); in al_serdes_25g_reg_write()
202 return -1; in al_serdes_25g_mailbox_send_cmd()
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H A Dal_hal_serdes_interface.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
120 * Parallel loopback from the PMA receive lane data ports, to the
121 * transmit lane data ports
178 * Tx de-emphasis parameters
183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
196 * Transmit Amplitude control signal. Used to define the full-scale
198 * 000 - Not Supported
199 * 001 - 952mVdiff-pkpk
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H A Dal_hal_serdes_hssp.c9 found at http://www.gnu.org/licenses/gpl-2.0.html
56 /* c(-1) configurations */
111 * Lane Rx rate change software flow disable
115 enum al_serdes_lane lane);
124 * Lane Rx rate change software flow enable if all conditions met
128 enum al_serdes_lane lane);
508 enum al_serdes_lane lane) in al_serdes_lane_rx_rate_change_sw_flow_en() argument
510 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 201, 0xfc); in al_serdes_lane_rx_rate_change_sw_flow_en()
511 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 202, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
512 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 203, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
[all …]
H A Dal_hal_serdes_internal_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
44 * Per lane register fields
47 * RX and TX lane hard reset
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
51 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM 2
57 * RX and TX lane hard reset control
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
[all …]
H A Dal_hal_serdes_hssp_internal_regs.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * Per lane register fields
46 * RX and TX lane hard reset
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
50 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM 2
56 * RX and TX lane hard reset control
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
60 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM 2
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
11 * 2. Redistributions in binary form must reproduce the above copyright
50 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
56 #define FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(x, i) (((x) >> (11 + ((i) - 1) * 6)) & 0x3F);
69 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4))
84 #define ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
106 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_VOP_DIV2P0_DET (1 << 2)
137 #define USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
183 #define HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c1 /*-
10 * 2. Redistributions in binary form must reproduce the above copyright
49 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
68 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4))
101 #define IOPHY_USB3_PAD_CTL2_RX_TERM_CNTL(x) (((x) & 0x0003) << 2)
124 #define USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
135 #define USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x) (((x) & 0x7) << 2)
170 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
171 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
190 {"nvidia,tegra124-xusb-padctl", 1},
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
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H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
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/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Duncore-other.json4 "Counter": "0,1,2,3",
11 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
12 "Counter": "0,1,2,3",
23 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
24 "Counter": "0,1,2,3",
36 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
60 "Counter": "0,1,2,3",
72 "Counter": "0,1,2,3",
84 "Counter": "0,1,2,3",
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/freebsd/sys/dev/hwpmc/
H A Dhwpmc_ppc970.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
12 * 2. Redistributions in binary form must reproduce the above copyright
46 ((r & ~(0x1f << (7 * (1 - i) + 1))) | (x << (7 * (1 - i) + 1)))
47 /* MMCR1 has 6 PMC*SEL items (PMC3->PMC8), in sequence. */
49 ((r & ~(0x1f << (5 * (7 - i) + 2))) | (x << (5 * (7 - i) + 2)))
56 * Encoding 00 000 -- Add byte lane bit counters
57 * MMCR1[24:31] -- select bit matching PMC being an adder.
59 * PMCxSEL: 1x -- select from byte lane: 10 == lower lane (0/1), 11 == upper
60 * lane (2/3).
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific Operands.
16 //===----------------------------------------------------------------------===//
108 return ((uint64_t)Imm) < 2;
158 // Register list of two D registers spaced by 2 (two sequential Q registers).
167 // Register list of three D registers spaced by 2 (three Q registers).
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3588-usbdp-phy
21 "#phy-cells":
24 - PHY_TYPE_USB3
25 - PHY_TYPE_DP
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H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
[all...]
H A Dphy-cadence-sierra.txt2 -----------------------
5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets: Must contain an entry for each in reset-names.
9 - reset-names: Must include "sierra_reset" and "sierra_apb".
13 - reg: register range for the PHY.
14 - #address-cells: Must be 1
15 - #size-cells: Must be 0
18 - clocks: Must contain an entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
[all …]
H A Dphy-mvebu-comphy.txt2 --------------------
12 - compatible: should be one of:
13 * "marvell,comphy-cp110" for Armada 7k/8k
14 * "marvell,comphy-a3700" for Armada 3700
15 - reg: should contain the COMPHY register(s) location(s) and length(s).
17 * 4 entries for Armada 3700 along with the corresponding reg-names
20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
23 - marvell,system-controller: should contain a phandle to the system
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp1 //===- X86InterleavedAccess.cpp -------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 /// optimization generating X86-specific instructions/intrinsics for
14 //===----------------------------------------------------------------------===//
43 /// X86-specific instructions/intrinsics.
44 /// E.g. A group of interleaving access loads (Factor = 2; accessing every
47 /// %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> poison, <0, 2, 4, 6>
50 /// Reference to the wide-load instruction of an interleaved access
57 /// Reference to the starting index of each user-shuffle.
[all …]

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