| /linux/tools/lib/ |
| H A D | list_sort.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Returns a list organized in an intermediate format suited
9 * to chaining of merge() calls: null-terminated, no reserved or
12 __attribute__((nonnull(2,3,4)))
14 struct list_head *a, struct list_head *b) in merge() argument
19 /* if equal, take 'a' -- important for sort stability */ in merge()
20 if (cmp(priv, a, b) <= 0) { in merge()
21 *tail = a; in merge()
22 tail = &a->next; in merge()
23 a = a->next; in merge()
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| /linux/lib/crypto/powerpc/ |
| H A D | md5-asm.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-offsets.h>
9 #include <asm/asm-compat.h>
40 PPC_STLU r1,-INT_FRAME_SIZE(r1); \
61 #define R_00_15(a, b, c, d, w0, w1, p, q, off, k0h, k0l, k1h, k1l) \ argument
69 add a,a,rT0; /* 1: a = a + f */ \
71 addis w1,w1,k1h; /* 2: wk = w + k */ \
72 add a,a,w0; /* 1: a = a + wk */ \
73 addi w1,w1,k1l; /* 2: wk = w + k' */ \
74 rotrwi a,a,p; /* 1: a = a rotl x */ \
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| /linux/lib/crypto/x86/ |
| H A D | sha256-ssse3-asm.S | 2 # Implement fast SHA-256 with SSSE3 instructions. (x86_64)
11 # This software is available to you under a choice of one of two
13 # General Public License (GPL) Version 2, available from the file
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
57 # Add reg to mem using reg-mem add and store
86 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
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|
| H A D | sha256-avx-asm.S | 2 # Implement fast SHA-256 with AVX1 instructions. (x86_64)
11 # This software is available to you under a choice of one of two
13 # General Public License (GPL) Version 2, available from the file
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 # This code is described in an Intel White-Paper:
41 # "Fast SHA-256 Implementations on Intel Architecture Processors"
47 # This code schedules 1 block at a time, with 4 lanes per block
58 # Add reg to mem using reg-mem add and store
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | uncore-power.json | 4 "Counter": "0,1,2,3",
7 …a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
39 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
57 "Counter": "0,1,2,3",
66 "Counter": "0,1,2,3",
74 "BriefDescription": "Core 2 C State Transition Cycles",
[all …]
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| /linux/tools/testing/selftests/drivers/net/mlxsw/ |
| H A D | devlink_trap_control.sh | 2 # SPDX-License-Identifier: GPL-2.0
4 # Test devlink-trap control trap functionality over mlxsw. Each registered
8 # +---------------------------------+
15 # | | default via 2001:db8:1::2 |
16 # +----|----------------------------+
18 # +----|----------------------------------------------------------------------+
22 # | 2001:db8:1::2/64 |
24 # | 2001:db8:2::2/64 |
28 # +----|----------------------------------------------------------------------+
30 # +----|----------------------------+
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-rgb.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
9 These formats encode each pixel as a triplet of RGB values. They are packed
12 bits required to store a pixel is not aligned to a byte boundary, the data is
20 or a permutation thereof, collectively referred to as alpha formats) depend on
22 (including capture queues of mem-to-mem devices) fill the alpha component in
24 a meaningful value. Otherwise, when the device doesn't capture an alpha channel
25 but can set the alpha bit to a user-configurable value, the
26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
28 the value specified by that control. Otherwise a corresponding format without
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| /linux/drivers/input/serio/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 * standard AT keyboard and PS/2 mouse *
17 To compile this driver as a module, choose M here: the
24 the architecture might use a PC serio device (i8042) to
34 i8042 is the chip over which the standard AT keyboard and PS/2
40 To compile this driver as a module, choose M here: the
55 To compile this driver as a module, choose M here: the
62 Say Y here if you have a Texas Instruments TravelMate notebook
63 equipped with the ct82c710 chip and want to use a mouse connected
68 To compile this driver as a module, choose M here: the
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | cache.json | 111 … prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",
114 …o prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"
117 …2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This even…
120 …2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This even…
123 …dless of whether they allocate. If either the core is configured without a per-core L2 or the clus…
126 …dless of whether they allocate. If either the core is configured without a per-core L2 or the clus…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 … streaming mode. This event counts for each cycle where the core is in write-streaming mode and no…
150 … streaming mode. This event counts for each cycle where the core is in write-streaming mode and no…
[all …]
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| /linux/drivers/input/mouse/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 Say Y here, and a list of supported mice will be displayed.
17 tristate "PS/2 mouse"
24 Say Y here if you have a PS/2 mouse connected to your system. This
25 includes the standard 2 or 3-button PS/2 mouse, as well as PS/2
30 in a specialized Xorg/XFree86 driver at:
32 and a new version of GPM at:
39 To compile this driver as a module, choose M here: the
43 bool "ALPS PS/2 mouse protocol extension" if EXPERT
47 Say Y here if you have an ALPS PS/2 touchpad connected to
[all …]
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| /linux/Documentation/filesystems/ |
| H A D | configfs.rst | 2 Configfs - Userspace-driven Kernel Object Configuration
16 configfs is a ram-based filesystem that provides the converse of
17 sysfs's functionality. Where sysfs is a filesystem-based view of
18 kernel objects, configfs is a filesystem-based manager of kernel
21 With sysfs, an object is created in kernel (for example, when a device
24 readdir(3)/read(2). It may allow some attributes to be modified via
25 write(2). The important point is that the object is created and
27 representation, and sysfs is merely a window on all this.
29 A configfs config_item is created via an explicit userspace operation:
30 mkdir(2). It is destroyed via rmdir(2). The attributes appear at
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| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3",
7 "PEBS": "2",
13 "Counter": "0,1,2,3",
16 "PEBS": "2",
23 "Counter": "0,1,2,3",
26 "PEBS": "2",
33 "Counter": "0,1,2,3",
36 "PEBS": "2",
43 "Counter": "0,1,2,3",
46 "PEBS": "2",
[all …]
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| /linux/Documentation/filesystems/spufs/ |
| H A D | spufs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 spufs - the SPU file system
20 The file system provides a name space similar to posix shared memory or
22 can use spu_create(2) to establish SPU contexts in the spufs root.
24 Every SPU context is represented by a directory containing a predefined
26 logical SPU. Users can change permissions on those files, but not actu-
43 The files in spufs mostly follow the standard behavior for regular sys-
44 tem calls like read(2) or write(2), but often support only a subset of
49 All files that support the read(2) operation also support readv(2) and
50 all files that support the write(2) operation also support writev(2).
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| /linux/tools/testing/selftests/drivers/net/mlxsw/spectrum-2/ |
| H A D | tc_flower.sh | 2 # SPDX-License-Identifier: GPL-2.0
4 # This test is for checking the A-TCAM and C-TCAM operation in Spectrum-2.
15 NUM_NETIFS=2
47 local cmd=$2
49 perf record -q -e $tracepoint $cmd
56 local seconds=$2
58 perf record -a -q -e $tracepoint sleep $seconds
66 local perf_output=`perf script -F trace:event,trace`
67 return `echo $perf_output | grep "$tracepoint:" | wc -l`
73 local count=$2
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| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | uncore-power.json | 4 "Counter": "0,1,2,3",
7 …a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
39 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
57 "Counter": "0,1,2,3",
66 "Counter": "0,1,2,3",
75 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | frontend.json | 3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
4 "Counter": "0,1,2,3",
7 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
13 "Counter": "0,1,2,3",
16 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a thre
20 { global() object
[all...] |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav…
13 "Counter": "0,1,2,3",
16 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (…
21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav…
22 "Counter": "0,1,2,3",
27 …"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (…
32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res…
33 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | frontend.json | 3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
4 "Counter": "0,1,2,3",
7 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
13 "Counter": "0,1,2,3",
16 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a thre
20 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | frontend.json | 3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
4 "Counter": "0,1,2,3",
7 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
13 "Counter": "0,1,2,3",
16 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a thre
20 { global() object
[all...] |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav…
13 "Counter": "0,1,2,3",
16 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (…
21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav…
22 "Counter": "0,1,2,3",
27 …"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (…
32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res…
33 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3",
17 … the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unk…
24 "Counter": "0,1,2,3",
27 … the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Leng…
34 "Counter": "0,1,2,3",
42 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
43 "Counter": "0,1,2,3",
46 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | uncore-power.json | 4 "Counter": "0,1,2,3",
7 …a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was e…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
39 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
57 "Counter": "0,1,2,3",
66 "Counter": "0,1,2,3",
75 "Counter": "0,1,2,3",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | uncore-power.json | 4 "Counter": "0,1,2,3",
7 …a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was e…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
39 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
57 "Counter": "0,1,2,3",
66 "Counter": "0,1,2,3",
75 "Counter": "0,1,2,3",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | frontend.json | 3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
4 "Counter": "0,1,2,3",
7 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
13 "Counter": "0,1,2,3",
16 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a thre
20 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3",
7 "PEBS": "2",
13 "Counter": "0,1,2,3",
16 "PEBS": "2",
23 "Counter": "0,1,2,3",
26 "PEBS": "2",
33 "Counter": "0,1,2,3",
36 "PEBS": "2",
43 "Counter": "0,1,2,3",
46 "PEBS": "2",
[all …]
|