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/freebsd/share/examples/BSD_daemon/
H A Dbeastie.svg1 <?xml version="1.0" encoding="UTF-8"?>
3 …,0%,0%);stroke-opacity:1;stroke-miterlimit:10;stroke-linecap:butt;stroke-linejoin:miter;fill:none;…
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8 …4 3 l 10 6 l 16 10 l 19 11 l 20 12 l 18 11 l 17 9 l 14 8 l 13 7 l 10 5 l 11 5 l 22 10 l 11 4 l 12 …
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10 …2 1 l 9 3 l 13 4 l 13 5 l 10 3 l 9 3 l 8 3 l 9 3 l 10 3 l 9 3 l 9 3 l 9 2 l 8 2 l 9 2 l 10 1 l 9 1…
11 …-6 -7 l -6 -7 l -8 -7 l -8 -7 l -8 -8 l -9 -7 l -8 -7 l -7 -6 l -8 -6 l -9 -7 l -9 -6 l -9 -7 l -1…
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/freebsd/contrib/netbsd-tests/ipf/expected/
H A Dn1_61 > zx0 ip6/0 1 0 255 10:1:1:0:0:0:0:0 > 10:1:1:0:0:0:0:2
2 > zx0 ip6/0 1 0 255 10:0:0:0:0:2:2:2 > 10:1:1:0:0:0:0:2
3 > zx0 ip6/0 1 0 255 10:1:1:0:0:0:0:2 > 10:1:1:0:0:0:0:1
4 > zx0 ip6/0 20 0 6 10:1:1:0:0:0:0:2,1025 > 10:1:1:0:0:0:0:1,1025
5 > zx0 ip6/0 20 0 6 10:1:1:0:0:0:0:2,1026 > 10:1:1:0:0:0:0:1,1025
6 > zx0 ip6/0 1 0 255 10:0:0:0:0:2:2:1 > 10:1:2:0:0:0:0:1
7 > zx0 ip6/0 1 0 255 10:0:0:0:0:2:2:2 > 10:1:2:0:0:0:0:1
8 < zx0 ip6/0 1 0 255 10:1:1:0:0:0:0:1 > 10:1:1:0:0:0:0:2
9 < zx0 ip6/0 1 0 255 10:1:1:0:0:0:0:2 > 10:1:1:0:0:0:0:1
10 < zx0 ip6/0 1 0 255 10:0:0:0:0:2:2:1 > 10:0:0:0:0:2:1:1
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H A Dn5_61 > zx0 ip6/0 1 0 255 10:1:1:0:0:0:0:0 > 10:1:1:0:0:0:0:2
2 > zx0 ip6/0 1 0 255 10:0:0:0:0:2:2:2 > 10:1:1:0:0:0:0:2
3 > zx0 ip6/0 1 0 255 10:1:1:0:0:0:0:2 > 10:1:1:0:0:0:0:1
4 > zx0 ip6/0 20 0 6 10:1:1:0:0:0:0:2,1025 > 10:1:1:0:0:0:0:1,1025
5 > zx0 ip6/0 20 0 6 10:1:1:0:0:0:0:2,1026 > 10:1:1:0:0:0:0:1,1025
6 > zx0 ip6/0 1 0 255 10:0:0:0:0:2:2:1 > 10:1:2:0:0:0:0:1
7 > zx0 ip6/0 1 0 255 10:0:0:0:0:2:2:2 > 10:1:2:0:0:0:0:1
8 < zx0 ip6/0 1 0 255 10:1:1:0:0:0:0:1 > 10:1:1:0:0:0:0:2
9 < zx0 ip6/0 1 0 255 10:1:1:0:0:0:0:2 > 10:1:1:0:0:0:0:1
10 < zx0 ip6/0 1 0 255 10:0:0:0:0:2:2:1 > 10:0:0:0:0:2:1:1
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/freebsd/share/doc/papers/jail/
H A Djail01.fig8 -2
9 1200 2
12 2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 2
14 2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 2
16 -6
17 2 1 0 2 0 7 100 0 -1 0.000 0 2 -1 0 0 2
19 2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 2
21 2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 2
23 2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 2
25 2 1 0 2 0 7 100 0 -1 0.000 0 0 -1 0 0 2
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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600-c64x.pl2 # Copyright 2017-2020 The OpenSSL Project Authors. All Rights Reserved.
16 # [ABI- and endian-neutral] Keccak-1600 for C64x.
21 # with bit interleaving. 64-bit values are simply split between A- and
22 # B-files, with A-file holding least significant halves. This works
23 # out perfectly, because all operations including cross-communications
25 # [incredible for a 32-bit processor] 10.9 cycles per processed byte
26 # for r=1088, which corresponds to SHA3-256. This is >15x faster than
27 # compiler-generated KECCAK_1X_ALT code, and >10x than other variants.
30 my @A = map([ $_, ($_+1), ($_+2), ($_+3), ($_+4) ], (5,10,16,21,26));
31 $A[1][4] = 31; # B14 is reserved, A14 is used as iota[]
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H A Dkeccak1600-avx2.pl2 # Copyright 2017-2023 The OpenSSL Project Authors. All Rights Reserved.
16 # Keccak-1600 for AVX2.
22 # other than A[0][0] in magic order into 6 [256-bit] registers, *each
23 # dedicated to one axis*, Pi permutation is reduced to intra-register
29 # [4][4] [3][3] [2][2] [1][1]<-+
30 # [0][4] [0][3] [0][2] [0][1]<-+
31 # [3][0] [1][0] [4][0] [2][0] |
32 # [4][3] [3][1] [2][4] [1][2] |
33 # [3][4] [1][3] [4][2] [2][1] |
34 # [2][3] [4][1] [1][4] [3][2] |
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H A Dkeccak1600-ppc64.pl2 # Copyright 2017-2020 The OpenSSL Project Authors. All Rights Reserved.
16 # Keccak-1600 for PPC64.
21 # *any* PPC64. Then PowerISA 2.07 adds 2x64-bit vector rotate, and
35 # (*) Corresponds to SHA3-256. Percentage after slash is improvement
36 # over gcc-4.x-generated KECCAK_1X_ALT code. Newer compilers do
47 $LRSAVE =2*$SIZE_T;
55 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
56 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
57 die "can't locate ppc-xlate.pl";
68 my @A = map([ "r$_", "r".($_+1), "r".($_+2), "r".($_+3), "r".($_+4) ],
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H A Dkeccak1600-armv8.pl2 # Copyright 2017-2020 The OpenSSL Project Authors. All Rights Reserved.
16 # Keccak-1600 for ARMv8.
22 # 64-bit lanes of vector registers can't be addressed as easily as in
23 # 32-bit mode. This means that 64-bit NEON is bound to be slower than
24 # 32-bit NEON, and this implementation is faster than 32-bit NEON on
31 # Add hardware-assisted ARMv8.2 implementation. It's KECCAK_1X_ALT
36 # support [yet?]. But lowest-level core procedure is prepared for it.
47 # Cortex-A53 13
48 # Cortex-A57 12
49 # X-Gene 14
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H A Dkeccak1600-s390x.pl2 # Copyright 2017-2020 The OpenSSL Project Authors. All Rights Reserved.
16 # Keccak-1600 for s390x.
22 # instead of actually unrolling the loop pair-wise I simply flip
31 # faster than compiler-generated code.
39 $SIZE_T=4;
48 my @A = map([ 8*$_, 8*($_+1), 8*($_+2), 8*($_+3), 8*($_+4) ], (0,5,10,15,20));
53 my ($src,$dst,$iotas) = map("%r$_",(2..4));
56 $stdframe=16*$SIZE_T+4*8;
63 [ 18, 2, 61, 56, 14 ]);
75 lg @C[0],$A[4][0]($src)
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H A Dkeccak1600-avx512vl.pl2 # Copyright 2017-2023 The OpenSSL Project Authors. All Rights Reserved.
16 # Keccak-1600 for AVX512VL.
21 # layout, but utilizes new 256-bit AVX512VL instructions. See AVX2
29 # Skylake-X 6.4/+47%
31 # (*) Corresponds to SHA3-256. Percentage after slash is improvement
32 # coefficient in comparison to scalar keccak1600-x86_64.pl.
34 # Digits in variables' names denote right-most coordinates:
37 $A01, # [0][4] [0][3] [0][2] [0][1] # %ymm1
38 $A20, # [3][0] [1][0] [4][0] [2][0] # %ymm2
39 $A31, # [2][4] [4][3] [1][2] [3][1] # %ymm3
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H A Dkeccak1600-armv4.pl2 # Copyright 2017-2020 The OpenSSL Project Authors. All Rights Reserved.
16 # Keccak-1600 for ARMv4.
20 # Non-NEON code is KECCAK_1X variant (see sha/keccak1600.c) with bit
22 # fast, but several times smaller, and is endian- and ISA-neutral. ISA
24 # be assembled even as Thumb-2. NEON code path is KECCAK_1X_ALT with
26 # in fact faster by 10-15% on some processors, and endian-neutral.
30 # Switch to KECCAK_2X variant for non-NEON code and merge almost 1/2
33 # minimizes re-loads from temporary storage, and merged rotates just
40 # 'eor a,b,c>>>(x-y)' and then merge-rotating 'a' in next operation
44 # is the keyword, i.e. "almost 1/2" is kind of complexity cap [for the
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/freebsd/contrib/sendmail/libmilter/docs/
H A Dfigure2.fig8 -2
9 1200 2
10 5 1 0 1 0 7 50 0 -1 0.000 0 0 1 0 2981.250 1200.000 2700 1050 3300 1200 2700 1350
13 2 2 0 1 1 7 50 0 -1 0.000 0 0 7 0 0 5
15 4 0 1 50 0 0 16 0.0000 4 195 2040 4350 1200 xxfi_header callback\001
16 -6
18 2 2 0 1 4 7 50 0 -1 0.000 0 0 7 0 0 5
20 4 0 4 50 0 0 16 0.0000 4 195 2040 4350 2550 xxfi_header callback\001
21 -6
23 2 2 0 2 4 7 50 0 -1 0.000 0 0 7 0 0 5
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVecFuncs.def1 //===-- VecFuncs.def - Library information -------------*- C++ -*-----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
27 // Floating-Point Arithmetic and Auxiliary Functions
28 TLI_DEFINE_VECFUNC("ceilf", "vceilf", FIXED(4), "_ZGV_LLVM_N4v")
29 TLI_DEFINE_VECFUNC("fabsf", "vfabsf", FIXED(4), "_ZGV_LLVM_N4v")
30 TLI_DEFINE_VECFUNC("llvm.fabs.f32", "vfabsf", FIXED(4), "_ZGV_LLVM_N4v")
31 TLI_DEFINE_VECFUNC("floorf", "vfloorf", FIXED(4), "_ZGV_LLVM_N4v")
32 TLI_DEFINE_VECFUNC("sqrtf", "vsqrtf", FIXED(4), "_ZGV_LLVM_N4v")
33 TLI_DEFINE_VECFUNC("llvm.sqrt.f32", "vsqrtf", FIXED(4), "_ZGV_LLVM_N4v")
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/freebsd/contrib/arm-optimized-routines/math/test/traces/
H A Dsincosf.txt159 -0x1.d7dbf4p-10
160 0x1.d7dbf4p-10
161 -0x1.3e4a7p-14
163 -0x1.088c36p-9
164 0x1.fd3378p-10
165 -0x1.7f293cp-14
167 -0x1.0c0774p-9
168 0x1.000dfep-9
169 -0x1.88f704p-14
171 -0x1.0c7494p-9
[all …]
H A Dexp.txt2 0x1.f9a012f44a109p-1
3 -0x1.87a0e64ca4704p-15
4 0x1.d2d48a18a7775p-1
5 0x1.bb1c1c3d91533p-1
6 -0x1.f99f18cd2896bp-16
7 0x1.58bb57317e405p-1
8 0x1.4a09091f7ebeep-1
9 -0x1.44718c44e91cfp-16
10 0x1.45fa2a0b71c2bp-1
11 0x1.38762d53b5588p-1
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td1 //===----------
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/freebsd/contrib/llvm-project/libcxx/include/__charconv/
H A Dtables.h1 // -*- C++ -*-
2 //===----------------------------------------------------------------------===//
6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 //===----------------------------------------------------------------------===//
32 …'0', '0', '0', '1', '0', '2', '0', '3', '0', '4', '0', '5', '0', '6', '0', '7', '1', '0', '1', '1'…
33 …'1', '3', '1', '4', '1', '5', '1', '6', '1', '7', '2', '0', '2', '1', '2', '2', '2', '3', '2', '4'…
34 …'2', '6', '2', '7', '3', '0', '3', '1', '3', '2', '3', '3', '3', '4', '3', '5', '3', '6', '3', '7'…
35 …'4', '1', '4', '2', '4', '3', '4', '4', '4', '5', '4', '6', '4', '7', '5', '0', '5', '1', '5', '2'…
36 …'5', '4', '5', '5', '5', '6', '5', '7', '6', '0', '6', '1', '6', '2', '6', '3', '6', '4', '6', '5'…
37 '6', '7', '7', '0', '7', '1', '7', '2', '7', '3', '7', '4', '7', '5', '7', '6', '7', '7'};
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/freebsd/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
H A Dtst.quantmany.d.out3 value ------------- Distribution ------------- count
6 2 |@@@@@@@@@@@@@@@@@@@@@@@@@@@ 2
7 4 | 0
9 2
10 value ------------- Distribution ------------- count
11 -4 | 0
12 -2 @@@@| -2
13 -1 | 0
16 2 |@@@@ 2
17 4 |@@@@@@@@@ 4
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H A Dtst.keysort.d.out2 Amsterdam 17 8 -3
3 Brisbane 14 7 -2
4 Melbourne 16 7 -2
5 Sydney 15 7 -2
6 London 13 6 -1
7 Prague 12 6 -1
14 Zurich 5 4 1
15 Shanghai 4 3 2
16 Dublin 3 2 3
17 London 2 2 3
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/freebsd/crypto/openssl/crypto/modes/asm/
H A Daes-gcm-armv8_64.pl2 # Copyright 2019-2023 The OpenSSL Project Authors. All Rights Reserved.
12 # derived from https://github.com/ARM-software/AArch64cryptolib, original
18 # Approach - assume we don't want to reload constants, so reserve ~half of vector register file for…
20 # main loop to act on 4 16B blocks per iteration, and then do modulo of the accumulated intermediat…
27 # | CTR block 4k+8 | AES block 4k+4 | GHASH block 4k+0 |
30 # | CTR block 4k+9 | AES block 4k+5 | GHASH block 4k+1 |
33 # | CTR block 4k+10| AES block 4k+6 | GHASH block 4k+2 |
36 # | CTR block 4k+11| AES block 4k+7 | GHASH block 4k+3 |
43 # Ensure previous generated intermediate hash is aligned and merged with result for GHASH 4k+0
45 # EOR res_curr (4k+0), res_curr (4k+0), low_acc
[all …]
/freebsd/sys/crypto/openssl/aarch64/
H A Daes-gcm-armv8_64.S1 /* Do not modify. This file is auto-generated from aes-gcm-armv8_64.pl. */
5 .arch armv8-a+crypto
9 .align 4
13 stp x19, x20, [sp, #-112]!
39 ld1 {v18.4s}, [x8], #16 //load rk0
41 sub x5, x5, #1 //byte_len - 1
53 ld1 {v19.4s}, [x8], #16 //load rk1
63 rev w9, w12 //CTR block 2
65 fmov d2, x10 //CTR block 2
66 orr x9, x11, x9, lsl #32 //CTR block 2
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/freebsd/crypto/openssl/test/recipes/10-test_bn_data/
H A Dbnshift.txt8 # These test vectors satisfy A * 2 = LShift1
18 LShift1 = -13116120bca5df64e13f314254
19 A = -988b0905e52efb2709f98a12a
24 LShift1 = -2622c241794bbec9c27e6284a8
25 A = -13116120bca5df64e13f314254
27 LShift1 = 4c458482f2977d9384fcc50950
30 LShift1 = -4c458482f2977d9384fcc50950
31 A = -2622c241794bbec9c27e6284a8
34 A = 4c458482f2977d9384fcc50951
36 LShift1 = -988b0905e52efb2709f98a12a2
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A Dpipeline.json18 "CollectPEBSRecord": "2",
19 "Counter": "0,1,2,3,4,5,6,7",
23 "PEBScounters": "0,1,2,3,4,5,6,7",
29 "CollectPEBSRecord": "2",
30 "Counter": "0,1,2,3,4,5,6,7",
34 "PEBScounters": "0,1,2,3,4,5,6,7",
35 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
41 "CollectPEBSRecord": "2",
42 "Counter": "0,1,2,3,4,5,6,7",
46 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DRISCVVTypes.def1 //===-- RISCVVTypes.def - Metadata for the RISC-V V types ------*- C++ -*--===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines various RISC-V V builtin types. The macros are:
11 // - RVV_TYPE(Name, Id, SingletonId)
15 // - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP,
17 // A RISC-V V scalable vector.
19 // - RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)
20 // An RISC-V V scalable mask.
24 // - Name is the name of the builtin type.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA55.td1 //==- AArch64SchedCortexA55.td - ARM Cortex-A55 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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