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2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration11 Copyright (c) 1999-2015 Cadence Design Systems Inc.40 /* Save area for non-coprocessor optional and custom (TIE) state: */45 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)62 * galign = group byte alignment (power of 2) (galign >= align)63 * align = register byte alignment (power of 2)66 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)68 * regnum = reg index in regfile, or special/TIE-user reg number[all …]
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration11 Copyright (c) 1999-2015 Cadence Design Systems Inc.63 /* Save area for non-coprocessor optional and custom (TIE) state: */68 #define XCHAL_TOTAL_SA_SIZE 48 /* with 16-byte align padding */81 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)82 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)85 * galign = group byte alignment (power of 2) (galign >= align)86 * align = register byte alignment (power of 2)89 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)91 * regnum = reg index in regfile, or special/TIE-user reg number[all …]
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration11 Copyright (c) 1999-2015 Cadence Design Systems Inc.35 #define XCHAL_CP_NUM 2 /* number of coprocessors */66 /* Save area for non-coprocessor optional and custom (TIE) state: */71 #define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)88 * galign = group byte alignment (power of 2) (galign >= align)89 * align = register byte alignment (power of 2)92 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)[all …]
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration11 Copyright (c) 1999-2014 Tensilica Inc.35 #define XCHAL_CP_NUM 2 /* number of coprocessors */66 /* Save area for non-coprocessor optional and custom (TIE) state: */71 #define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)88 * galign = group byte alignment (power of 2) (galign >= align)89 * align = register byte alignment (power of 2)92 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)[all …]
2 # SPDX-License-Identifier: GPL-2.016 [[ $(id -u) -eq 0 ]] || skip_test "Test must be run as root!"23 CGROUP2=$(mount -t cgroup2 | head -1 | awk -e '{print $3}')24 [[ -n "$CGROUP2" ]] || skip_test "Cgroup v2 mount point not found!"28 NR_CPUS=$(lscpu | grep "^CPU(s):" | sed -e "s/.*:[[:space:]]*//")29 [[ $NR_CPUS -lt 8 ]] && skip_test "Test needs at least 8 cpus available!"32 if [[ -c /dev/console && -w /dev/console ]]44 while [[ "$1" = -* ]]47 -v) ((VERBOSE++))49 [[ $DELAY_FACTOR -eq 1 ]] &&[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */6 #include <asm/feature-fixups.h>9 #include <asm/asm-compat.h>10 #include <asm/ppc-opcode.h>20 or 2,2,2 /* fixup will nop out this instruction */21 or 3,3,327 or 2,2,228 or 3,3,333 or 3,3,337 or 2,2,2 /* fixup will replace this with ftr_fixup_test2_alt */[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */14 #include <linux/kasan-tags.h>16 #include <asm/gpr-num.h>21 * C5.2, version:ARM DDI 0487A.f)22 * [20-19] : Op023 * [18-16] : Op124 * [15-12] : CRn25 * [11-8] : CRm26 * [7-5] : Op283 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/pinctrl/rockchip.h>7 #include "rockchip-pinconf.dtsi"15 /omit-if-no-ref/16 acodec_pins: acodec-pins {36 /omit-if-no-ref/37 audiopwm_lout: audiopwm-lout {43 /omit-if-no-ref/44 audiopwm_loutn: audiopwm-loutn {50 /omit-if-no-ref/[all …]
1 // SPDX-License-Identifier: GPL-2.08 * kernel, we can't go older than v5.2, though, because that's the first120 if (s->finalize) { in finalize_vcpu()121 feature = s->feature; in finalize_vcpu()129 #define CORE_REGS_XX_NR_WORDS 2130 #define CORE_SPSR_XX_NR_WORDS 2143 idx = (core_off - KVM_REG_ARM_CORE_REG(regs.regs[0])) / CORE_REGS_XX_NR_WORDS; in core_id_to_str()157 KVM_REG_ARM_CORE_REG(spsr[KVM_NR_SPSR - 1]): in core_id_to_str()158 idx = (core_off - KVM_REG_ARM_CORE_REG(spsr[0])) / CORE_SPSR_XX_NR_WORDS; in core_id_to_str()163 idx = (core_off - KVM_REG_ARM_CORE_REG(fp_regs.vregs[0])) / CORE_FPREGS_XX_NR_WORDS; in core_id_to_str()[all …]
3 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",4 "Counter": "0,1,2,3",12 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",13 "Counter": "0,1,2,3",21 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",22 "Counter": "0,1,2,3",30 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",31 "Counter": "0,1,2,3",39 …ccessfully inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ",40 "Counter": "0,1,2,3",[all …]
4 "Counter": "0,1,2,3",15 "Counter": "0,1,2,3",26 "Counter": "0,1,2,3",37 "Counter": "0,1,2,3",48 "Counter": "0,1,2,3",57 "BriefDescription": "ACT command issued by 2 cycle bypass",58 "Counter": "0,1,2,3",67 "BriefDescription": "CAS command issued by 2 cycle bypass",68 "Counter": "0,1,2,3",77 "BriefDescription": "PRE command issued by 2 cycle bypass",[all …]
4 "Counter": "0,1,2,3",15 "Counter": "0,1,2,3",26 "Counter": "0,1,2,3",36 "Counter": "0,1,2,3",46 "Counter": "0,1,2,3",24 { global() object 34 { global() object [all...]
4 "Counter": "0,1,2,3",15 "Counter": "0,1,2,3",26 "Counter": "0,1,2,3",36 "Counter": "0,1,2,3",46 "Counter": "0,1,2,3",55 "BriefDescription": "ACT command issued by 2 cycle bypass",56 "Counter": "0,1,2,3",64 "BriefDescription": "CAS command issued by 2 cycle bypass",65 "Counter": "0,1,2,3",73 "BriefDescription": "PRE command issued by 2 cycle bypass",[all …]
4 "Counter": "0,1,2,3",14 "Counter": "0,1,2,3",24 "Counter": "0,1,2,3",33 "BriefDescription": "ACT command issued by 2 cycle bypass",34 "Counter": "0,1,2,3",42 "BriefDescription": "CAS command issued by 2 cycle bypass",43 "Counter": "0,1,2,3",51 "BriefDescription": "PRE command issued by 2 cycle bypass",52 "Counter": "0,1,2,3",60 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions8 * it under the terms of the GNU General Public License version 2 as17 * assemblers both consider the SHA-512 instructions to be part of the20 * versions.) "sha3" doesn't make a lot of sense, since SHA-512 is part21 * of the SHA-2 family of algorithms, and also the Arm Architecture25 .arch armv8-a+sha328 * The SHA-512 round constants76 ld1 {v\rc1\().2d}, [x4], #1678 add v5.2d, v\rc0\().2d, v\in0\().2d[all …]
1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later3 .. _pixfmt-rgb:22 (including capture queues of mem-to-mem devices) fill the alpha component in25 but can set the alpha bit to a user-configurable value, the26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to31 :ref:`Output <output>` devices (including output queues of mem-to-mem devices44 - In all the tables that follow, bit 7 is the most significant bit in a byte.45 - 'r', 'g' and 'b' denote bits of the red, green and blue components54 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,57 for each component. For instance, the RGB565 format stores a pixel in a 16-bit[all …]
9 Addresses scanned: -13 Author: Samuel Mendoza-Jonas <sam@mendozajonas.com>17 -----------19 IR35221 is a Digital DC-DC Multiphase Converter23 -----------32 # echo ir35221 0x70 > /sys/bus/i2c/devices/i2c-4/new_device36 ----------------44 curr[2-3]_label "iout[1-2]"45 curr[2-3]_input Measured output current46 curr[2-3]_crit Critical maximum current[all …]
4 "Counter": "0,1,2,3",12 "Counter": "0,1,2,3",22 "Counter": "0,1,2,3",31 "Counter": "0,1,2,3",41 "Counter": "0,1,2,3",49 …"BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts th…50 "Counter": "0,1,2,3",59 "Counter": "0,1,2,3",68 "Counter": "0,1,2,3",77 "Counter": "0,1,2,3",[all …]
2 # SPDX-License-Identifier: GPL-2.09 # +-----------------------+13 # +----|------------------+15 # +----|----------------------------------------------------------------------+17 # | +--|--------------------------------------------------------------------+ |21 # | | local 2001:db8:2::1 | |22 # | | remote 2001:db8:2::{2..21} | |24 # | +-----------------------------------------------------------------------+ |26 # | 2001:db8:2::0/64 via 2001:db8:3::2 |29 # | | 2001:db8:3::1/64 |[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016 - 2017 Xilinx, Inc.11 #include <linux/clk-provider.h>17 #include <linux/mfd/syscon/xlnx-vcu.h>23 #include <dt-bindings/clock/xlnx-vcu.h>28 #define VCU_PLL_CTRL_PWR_POR BIT(2)29 #define VCU_PLL_CTRL_BYPASS BIT(3)34 #define VCU_PLL_CFG_RES GENMASK(3, 0)51 * struct xvcu_device - Xilinx VCU init device structure84 * struct xvcu_pll_cfg - Helper data[all …]
4 "Counter": "0,1,2,3",12 "Counter": "0,1,2,3",21 "Counter": "0,1,2,3",30 "Counter": "0,1,2,3",39 "Counter": "0,1,2,3",47 …"BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts th…48 "Counter": "0,1,2,3",57 "Counter": "0,1,2,3",66 "Counter": "0,1,2,3",75 "Counter": "0,1,2,3",[all …]
4 "Counter": "0,1,2,3",12 "Counter": "0,1,2,3",23 "Counter": "0,1,2,3",31 "Counter": "0,1,2,3",39 "Counter": "0,1,2,3",47 "Counter": "0,1,2,3",55 "Counter": "0,1,2,3",63 "Counter": "0,1,2,3",71 "Counter": "0,1,2,3",79 "Counter": "0,1,2,3",[all …]