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Searched +full:1 +full:x128b (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/misc/
H A Dxlnx,sd-fec.yaml26 maxItems: 1
62 maxItems: 1
77 Configures the DIN AXI stream where a value of 1
78 configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
79 of "4x128b".
81 enum: [ 1, 2, 4 ]
86 driven with a fixed value and is not present on the device, a value of 1
90 enum: [ 0, 1, 2 ]
94 Configures the DOUT AXI stream where a value of 1 configures a width of "1x128b",
95 2 a width of "2x128b" and 4 configures a width of "4x128b".
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_1_offset.h3185 …GC_CAC_PG_AGGR_LOWER 0x128b
3574 …ne mmDB_RENDER_CONTROL_BASE_IDX 1
3576 …ne mmDB_COUNT_CONTROL_BASE_IDX 1
3578 …ne mmDB_DEPTH_VIEW_BASE_IDX 1
3580 …ne mmDB_RENDER_OVERRIDE_BASE_IDX 1
3582 …ne mmDB_RENDER_OVERRIDE2_BASE_IDX 1
3584 …ne mmDB_HTILE_DATA_BASE_BASE_IDX 1
3586 …ne mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1
3588 …ne mmDB_DEPTH_SIZE_BASE_IDX 1
3590 …ne mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1
[all …]
H A Dgc_12_0_0_offset.h939 …e regSDMA0_VM_CTX_LO_BASE_IDX 1
941 …e regSDMA0_VM_CTX_HI_BASE_IDX 1
943 …e regSDMA0_ACTIVE_FCN_ID_BASE_IDX 1
945 …e regSDMA0_VIRT_RESET_REQ_BASE_IDX 1
947 …e regSDMA0_VM_CNTL_BASE_IDX 1
949 …e regSDMA0_MCU_CNTL_BASE_IDX 1
951 …e regSDMA0_IC_BASE_LO_BASE_IDX 1
953 …e regSDMA0_IC_BASE_HI_BASE_IDX 1
955 …e regSDMA0_IC_BASE_CNTL_BASE_IDX 1
957 …e regSDMA0_IC_OP_CNTL_BASE_IDX 1
[all …]
H A Dgc_11_0_3_offset.h1747 …e regSDMA0_UCODE_ADDR_BASE_IDX 1
1749 …e regSDMA0_UCODE_DATA_BASE_IDX 1
1751 …e regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX 1
1753 …e regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX 1
1755 …e regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX 1
1757 …e regSDMA0_VM_CTX_LO_BASE_IDX 1
1759 …e regSDMA0_VM_CTX_HI_BASE_IDX 1
1761 …e regSDMA0_ACTIVE_FCN_ID_BASE_IDX 1
1763 …e regSDMA0_VM_CTX_CNTL_BASE_IDX 1
1765 …e regSDMA0_VIRT_RESET_REQ_BASE_IDX 1
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_2_offset.h33 …ne mmVGA_RENDER_CONTROL_BASE_IDX 1
35 …ne mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
37 …ne mmVGA_MODE_CONTROL_BASE_IDX 1
39 …ne mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
41 …ne mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
43 …ne mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
45 …ne mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
47 …ne mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
49 …ne mmVGA_HDP_CONTROL_BASE_IDX 1
51 …ne mmVGA_CACHE_CONTROL_BASE_IDX 1
[all …]
H A Ddcn_3_0_0_offset.h15 …ne mmVGA_RENDER_CONTROL_BASE_IDX 1
17 …ne mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
19 …ne mmVGA_MODE_CONTROL_BASE_IDX 1
21 …ne mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
23 …ne mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
25 …ne mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
27 …ne mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
29 …ne mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
31 …ne mmVGA_HDP_CONTROL_BASE_IDX 1
33 …ne mmVGA_CACHE_CONTROL_BASE_IDX 1
[all …]