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/linux/arch/arm64/crypto/
H A Dsm4-ce-ccm-core.S17 .irp b, 0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 16, 24, 25, 26, 27, 28, 29, 30, 31
32 mov vctr.d[1], x8; \
34 adds x8, x8, #1; \
72 sub w3, w3, #1
132 inc_le128(v8) /* +0 */
133 inc_le128(v9) /* +1 */
139 SM4_CRYPT_BLK2(v8, RMAC)
140 eor v8.16b, v8.16b, v0.16b
152 st1 {v8.16b-v11.16b}, [x1], #64
164 inc_le128(v8)
[all …]
H A Dsm4-ce-cipher-core.S6 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8
19 ld1 {v8.4s}, [x2]
21 CPU_LE( rev32 v8.16b, v8.16b )
23 sm4e v8.4s, v0.4s
24 sm4e v8.4s, v1.4s
25 sm4e v8.4s, v2.4s
26 sm4e v8.4s, v3.4s
27 sm4e v8.4s, v4.4s
28 sm4e v8.4s, v5.4s
29 sm4e v8.4s, v6.4s
[all …]
H A Dsm4-ce-core.S17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
146 sub w3, w3, #1;
195 sub w4, w4, #1
233 rev32 v8.16b, v0.16b
242 SM4_CRYPT_BLK8_BE(v8, v9, v10, v11, v12, v13, v14, v15)
244 eor v8.16b, v8.16b, RIV.16b
253 st1 {v8.16b-v11.16b}, [x1], #64
270 rev32 v8.16b, v0.16b
275 SM4_CRYPT_BLK4_BE(v8, v9, v10, v11)
277 eor v8.16b, v8.16b, RIV.16b
[all …]
H A Dsm3-ce-core.S12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
45 sm3ss1 v5.4s, v8.4s, \t0\().4s, v9.4s
46 shl \t1\().4s, \t0\().4s, #1
48 sm3tt1\ab v8.4s, v5.4s, v10.4s, \i
63 round \ab, \s0, v12, v11, 1
79 ld1 {v8.4s-v9.4s}, [x0]
80 rev64 v8.4s, v8.4s
82 ext v8.16b, v8.16b, v8.16b, #8
90 sub w2, w2, #1
92 mov v15.16b, v8.16b
[all …]
H A Daes-neon.S24 tbnz \reg, #1, \lbl
30 shl \out, \in, #1
84 mul_by_x2 v8.16b, \in\().16b, v9.16b, v12.16b
85 eor \in\().16b, \in\().16b, v8.16b
86 rev32 v8.8h, v8.8h
87 eor \in\().16b, \in\().16b, v8.16b
90 mul_by_x v9.16b, \in\().16b, v8.16b, v12.16b
91 rev32 v8.8h, \in\().8h
92 eor v8.16b, v8.16b, v9.16b
93 eor \in\().16b, \in\().16b, v8.16b
[all …]
H A Dsha3-ce-core.S3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
52 ld1 {v24.1d}, [x8]
54 0: sub w2, w2, #1
[all …]
H A Daes-neonbs-core.S339 \t0, \t1, \t2, \t3, \t4, \t5, \t6, \t7, 1
360 swapmove_2x \x0, \x1, \x2, \x3, 1, \t0, \t2, \t3
361 swapmove_2x \x4, \x5, \x6, \x7, 1, \t0, \t2, \t3
386 ld1 {v17.4s}, [x1], #16 // load round 1 key
388 movi v8.16b, #0x01 // bit masks
398 sub x2, x2, #1
405 cmtst v0.16b, v7.16b, v8.16b
418 subs x2, x2, #1
439 tbl v0.16b, {v10.16b}, v8.16b
441 tbl v1.16b, {v11.16b}, v8.16b
[all …]
H A Daes-modes.S76 subs w4, w4, #1
106 subs w4, w4, #1
163 subs w4, w4, #1
190 ld1 {v4.16b}, [x1], #16 /* get 1 ct block */
198 ld1 {v5.16b}, [x1], #16 /* reload 1 ct block */
199 ld1 {cbciv.16b}, [x1], #16 /* reload 1 ct block */
211 ld1 {cbciv.16b}, [x1], #16 /* reload 1 ct block */
228 subs w4, w4, #1
347 umov IV_PART, vctr.d[1]
360 * Set up the counter values in v0-v{MAX_STRIDE-1}.
[all …]
/linux/Documentation/hwmon/
H A Dlochnagar.rst31 power1_average_interval Power averaging time input valid from 1 to 1708mS
33 in1_input Measured voltage for 1V8 DSP (milliVolts)
34 in1_label "1V8 DSP"
35 curr2_input Measured current for 1V8 DSP (milliAmps)
36 curr2_label "1V8 DSP"
37 power2_average Measured average power for 1V8 DSP (microWatts)
38 power2_average_interval Power averaging time input valid from 1 to 1708mS
39 power2_label "1V8 DSP"
40 in2_input Measured voltage for 1V8 CDC (milliVolts)
41 in2_label "1V8 CDC"
[all …]
/linux/arch/sh/boards/mach-hp6xx/
H A Dsetup.c31 [1] = {
44 .id = -1,
51 .id = -1,
57 u8 v8; in dac_audio_start() local
65 v8 = inb(PKDR); in dac_audio_start()
66 v8 &= ~PKDR_SPEAKER; in dac_audio_start()
67 outb(v8, PKDR); in dac_audio_start()
75 u8 v8; in dac_audio_stop() local
83 v8 = inb(PKDR); in dac_audio_stop()
84 v8 |= PKDR_SPEAKER; in dac_audio_stop()
[all …]
/linux/lib/crc/powerpc/
H A Dcrc-vpmsum-template.S101 vspltisw v0,-1
106 /* Get the initial value into v8 */
107 vxor v8,v8,v8
108 MTVRD(v8, R3)
110 vsldoi v8,zeroes,v8,8 /* shift into bottom 32 bits */
112 vsldoi v8,v8,zeroes,4 /* shift into top 32 bits */
127 1: lis r7,MAX_SIZE@h
148 addi r7,r7,-1
172 cmpdi r0,1
195 vxor v16,v16,v8
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dnvidia,tegra20-sdhci.yaml43 maxItems: 1
46 maxItems: 1
53 minItems: 1
57 minItems: 1
70 maxItems: 1
83 maxItems: 1
112 nvidia,pad-autocal-pull-down-offset-1v8:
117 nvidia,pad-autocal-pull-down-offset-1v8-timeout:
140 nvidia,pad-autocal-pull-up-offset-1v8:
145 nvidia,pad-autocal-pull-up-offset-1v8-timeout:
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dfixed-regulator.yaml61 maxItems: 1
64 maxItems: 1
71 maxItems: 1
78 maxItems: 1
87 maxItems: 1
111 maxItems: 1
125 reg_1v8: regulator-1v8 {
127 regulator-name = "1v8";
137 reg_1v8_clk: regulator-1v8-clk {
139 regulator-name = "1v8";
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-puma-haikou-video-demo.dtso28 cam_afvdd_2v8: regulator-cam-afvdd-2v8 {
33 regulator-name = "cam-afvdd-2v8";
37 cam_avdd_2v8: regulator-cam-avdd-2v8 {
42 regulator-name = "cam-avdd-2v8";
46 cam_dovdd_1v8: regulator-cam-dovdd-1v8 {
51 regulator-name = "cam-dovdd-1v8";
55 cam_dvdd_1v2: regulator-cam-dvdd-1v2 {
61 regulator-name = "cam-dvdd-1v2";
98 #address-cells = <1>;
111 reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>;
[all …]
H A Dpx30-ringneck-haikou-video-demo.dtso28 cam_afvdd_2v8: regulator-cam-afvdd-2v8 {
33 regulator-name = "cam-afvdd-2v8";
37 cam_avdd_2v8: regulator-cam-avdd-2v8 {
42 regulator-name = "cam-avdd-2v8";
46 cam_dovdd_1v8: regulator-cam-dovdd-1v8 {
51 regulator-name = "cam-dovdd-1v8";
55 cam_dvdd_1v2: regulator-cam-dvdd-1v2 {
61 regulator-name = "cam-dvdd-1v2";
99 <2 RK_PB3 1 &pcfg_pull_none_12ma>;
111 #address-cells = <1>;
[all …]
/linux/arch/powerpc/lib/
H A Dmemcpy_power7.S11 /* 0 == don't use VMX, 1 == use VMX */
42 bf cr7*4+3,1f
44 addi r4,r4,1
46 addi r3,r3,1
48 1: bf cr7*4+2,2f
54 2: bf cr7*4+1,3f
136 6: bf cr7*4+1,7f
191 12: bf cr7*4+1,13f
232 * 1 for the store side.
236 ori r9,r9,1 /* stream=1 */
[all …]
H A Dcopyuser_power7.S11 /* 0 == don't use VMX, 1 == use VMX */
98 bf cr7*4+3,1f
100 addi r4,r4,1
102 addi r3,r3,1
104 1: bf cr7*4+2,2f
110 2: bf cr7*4+1,3f
192 6: bf cr7*4+1,7f
247 12: bf cr7*4+1,13f
286 * 1 for the store side.
290 ori r9,r9,1 /* stream=1 */
[all …]
/linux/tools/testing/selftests/powerpc/copyloops/
H A Dmemcpy_power7.S11 /* 0 == don't use VMX, 1 == use VMX */
42 bf cr7*4+3,1f
44 addi r4,r4,1
46 addi r3,r3,1
48 1: bf cr7*4+2,2f
54 2: bf cr7*4+1,3f
136 6: bf cr7*4+1,7f
191 12: bf cr7*4+1,13f
232 * 1 for the store side.
236 ori r9,r9,1 /* stream=1 */
[all …]
H A Dcopyuser_power7.S11 /* 0 == don't use VMX, 1 == use VMX */
98 bf cr7*4+3,1f
100 addi r4,r4,1
102 addi r3,r3,1
104 1: bf cr7*4+2,2f
110 2: bf cr7*4+1,3f
192 6: bf cr7*4+1,7f
247 12: bf cr7*4+1,13f
286 * 1 for the store side.
290 ori r9,r9,1 /* stream=1 */
[all …]
/linux/arch/sparc/math-emu/
H A Dmath_32.c31 * These are defined in the third layer of macros: op-1.h, op-2.h
33 * of 1,2 and 4 machine words respectively. [For example, on sparc64
35 * constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
47 * SPARC architecture manual V9, and what I really want is V8...
50 * has to be emulated on V8). So I think I'm going to have
86 #define FSQRTQ 0x02b /* v8 */
87 #define FADDQ 0x043 /* v8 */
88 #define FSUBQ 0x047 /* v8 */
89 #define FMULQ 0x04b /* v8 */
90 #define FDIVQ 0x04f /* v8 */
[all …]
/linux/lib/crypto/arm64/
H A Dchacha-neon-core.S67 // x1 = shuffle32(x1, MASK(0, 3, 2, 1))
69 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
71 // x3 = shuffle32(x3, MASK(2, 1, 0, 3))
96 // x1 = shuffle32(x1, MASK(2, 1, 0, 3))
98 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
100 // x3 = shuffle32(x3, MASK(0, 3, 2, 1))
111 // x1: 1 data block output, o
112 // x2: 1 data block input, i
120 ld1 {v8.4s-v11.4s}, [x0]
127 add v0.4s, v0.4s, v8.4s
[all …]
/linux/arch/arm64/boot/dts/arm/
H A DMakefile3 foundation-v8.dtb foundation-v8-psci.dtb \
4 foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb
7 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-coresight.dtsi78 #address-cells = <1>;
89 port@1 {
90 reg = <1>;
147 #address-cells = <1>;
158 port@1 {
159 reg = <1>;
380 compatible = "arm,coresight-cti-v8-arch",
391 /* CTI - CPU-1 */
393 compatible = "arm,coresight-cti-v8-arch",
406 compatible = "arm,coresight-cti-v8-arch",
[all …]
/linux/lib/raid6/
H A Drvv.c31 p = dptr[z0 + 1]; /* XOR parity */ in raid6_rvv1_gen_syndrome_real()
42 for (d = 0; d < bytes; d += NSIZE * 1) { in raid6_rvv1_gen_syndrome_real()
53 for (z = z0 - 1 ; z >= 0 ; z--) { in raid6_rvv1_gen_syndrome_real()
66 "vsll.vi v3, v1, 1\n" in raid6_rvv1_gen_syndrome_real()
105 q = dptr[disks - 1]; /* RS syndrome */ in raid6_rvv1_xor_syndrome_real()
115 for (d = 0 ; d < bytes ; d += NSIZE * 1) { in raid6_rvv1_xor_syndrome_real()
127 for (z = z0 - 1; z >= start; z--) { in raid6_rvv1_xor_syndrome_real()
140 "vsll.vi v3, v1, 1\n" in raid6_rvv1_xor_syndrome_real()
154 for (z = start - 1; z >= 0; z--) { in raid6_rvv1_xor_syndrome_real()
164 "vsll.vi v3, v1, 1\n" in raid6_rvv1_xor_syndrome_real()
[all …]
/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti-platform.c17 /* Number of CTI signals in the v8 architecturally defined connection */
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
48 return -1; in of_cti_get_cpu_at_node()
53 return -1; in of_cti_get_cpu_at_node()
58 return (cpu < 0) ? -1 : cpu; in of_cti_get_cpu_at_node()
64 return -1; in of_cti_get_cpu_at_node()
78 return -1; in cti_plat_get_cpu_at_node()
170 * Create an architecturally defined v8 connection
186 "ARM v8 architectural CTI connection: missing cpu\n"); in cti_plat_create_v8_connections()
191 /* Allocate the v8 cpu connection memory */ in cti_plat_create_v8_connections()
[all …]

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