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/freebsd/crypto/openssl/crypto/aes/asm/
H A Dbsaes-armv8.pl15 $0 =~ m/(.*[\/\\])[^\/\\]+$/; my $dir=$1;
87 sub x10, x10, #1
88 eor v0.16b, v0.16b, v8.16b
89 eor v1.16b, v1.16b, v8.16b
90 eor v2.16b, v2.16b, v8.16b
91 eor v4.16b, v4.16b, v8.16b
92 eor v3.16b, v3.16b, v8.16b
93 eor v5.16b, v5.16b, v8.16b
98 eor v6.16b, v6.16b, v8.16b
99 eor v7.16b, v7.16b, v8.16b
[all …]
H A Dvpaes-armv8.pl46 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
231 and x11, x11, #~(1<<6) // and \$0x30, %r11 # ... mod 4
233 sub w8, w8, #1 // nr--
238 ushr v0.16b, v0.16b, #4 // vpsrlb \$4, %xmm0, %xmm0 # 1 = i
241 tbl v3.16b, {$invlo}, v0.16b // vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i
242 tbl v4.16b, {$invlo}, v1.16b // vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j
243 eor v3.16b, v3.16b, v5.16b // vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k
244 eor v4.16b, v4.16b, v5.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k
245 tbl v2.16b, {$invlo}, v3.16b // vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak
246 tbl v3.16b, {$invlo}, v4.16b // vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak
[all …]
H A Daes-riscv64-zvbb-zvkg-zvkned.pl19 # 1. Redistributions of source code must retain the above copyright
77 $V8, $V9, $V10, $V11, $V12, $V13, $V14, $V15,
90 addi $T0, $T0, -1
92 1:
95 addi $T0, $T0, -1
97 bnez $T0, 1b
113 # We could simplify the initialization steps if we have `block<=1`.
114 blt $LEN32, $T0, 1f
126 # Prepare GF(2^128) multiplier [1, x, x^2, x^3, ...] in v8.
129 # v2: [`1`, `1`, `1`, `1`, ...]
[all …]
/freebsd/sys/crypto/openssl/aarch64/
H A Dbsaes-armv8.S54 sub x10, x10, #1
55 eor v0.16b, v0.16b, v8.16b
56 eor v1.16b, v1.16b, v8.16b
57 eor v2.16b, v2.16b, v8.16b
58 eor v4.16b, v4.16b, v8.16b
59 eor v3.16b, v3.16b, v8.16b
60 eor v5.16b, v5.16b, v8.16b
65 eor v6.16b, v6.16b, v8.16b
66 eor v7.16b, v7.16b, v8.16b
70 ushr v8.2d, v0.2d, #1
[all …]
H A Daes-gcm-armv8-unroll8_64.S26 mov v31.d[1], x15
30 sub x5, x5, #1 //byte_len - 1
32 …and x5, x5, #0xffffffffffffff80 //number of bytes to be processed in main loop (at least 1 byte m…
38 rev32 v1.16b, v30.16b //CTR block 1
39 add v30.4s, v30.4s, v31.4s //CTR block 1
70 aesmc v1.16b, v1.16b //AES block 1 - round 0
81 aesmc v3.16b, v3.16b //AES block 3 - round 1
84 aesmc v7.16b, v7.16b //AES block 7 - round 1
86 aesmc v5.16b, v5.16b //AES block 5 - round 1
88 aesmc v4.16b, v4.16b //AES block 4 - round 1
[all …]
H A Daes-gcm-armv8_64.S41 sub x5, x5, #1 //byte_len - 1
48 fmov d1, x10 //CTR block 1
51 add w12, w12, #1 //increment rev_ctr32
55 rev w9, w12 //CTR block 1
56 add w12, w12, #1 //CTR block 1
59 orr x9, x11, x9, lsl #32 //CTR block 1
62 fmov v1.d[1], x9 //CTR block 1
67 add w12, w12, #1 //CTR block 2
69 fmov v2.d[1], x9 //CTR block 2
75 add w12, w12, #1 //CTR block 3
[all …]
H A Dvpaes-armv8.S168 and x11, x11, #~(1<<6) // and $0x30, %r11 # ... mod 4
170 sub w8, w8, #1 // nr--
175 ushr v0.16b, v0.16b, #4 // vpsrlb $4, %xmm0, %xmm0 # 1 = i
178 tbl v3.16b, {v18.16b}, v0.16b // vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i
179 tbl v4.16b, {v18.16b}, v1.16b // vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j
180 eor v3.16b, v3.16b, v5.16b // vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k
181 eor v4.16b, v4.16b, v5.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k
182 tbl v2.16b, {v18.16b}, v3.16b // vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak
183 tbl v3.16b, {v18.16b}, v4.16b // vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak
232 ushr v8.16b, v15.16b, #4
[all …]
H A Dsm4-armv8.S173 1:
175 b.lt 1f
326 b.gt 1b
403 b.gt 1b
404 1:
406 b.lt 1f
425 b.ne 1b
426 1:
438 ld1 {v8.4s},[x4]
441 1:
[all …]
H A Dvpsm4-armv8.S87 cbnz w2,1f
89 1:
90 mov w7,v5.s[1]
119 subs x6,x6,#1
120 b.ne 1b
263 subs w11,w11,#1
354 eor v8.16b,v8.16b,v13.16b
359 eor v15.16b,v15.16b,v8.16b
419 eor v15.16b,v8.16b,v9.16b
535 subs w11,w11,#1
[all …]
H A Darmv8-mont.S42 ldp x7,x8,[x1],#16 // ap[0..1]
46 ldp x13,x14,[x3],#16 // np[0..1]
51 mul x10,x8,x9 // ap[1]*bp[0]
59 mul x16,x14,x15 // np[1]*m1
69 // by adding -1 to x6. That's what next instruction does.
70 subs xzr,x6,#1 // (*)
91 str x12,[x22],#8 // tp[j-1]
104 sub x20,x5,#8 // i=num-1
120 mul x10,x8,x9 // ap[1]*bp[i]
130 mul x16,x14,x15 // np[1]*m1
[all …]
H A Dchacha-armv8.S16 .long 1,2,3,4
86 sub x4,x4,#1
237 add x28,x28,#1 // increment counter
260 sub x0,x0,#1
292 add x2,x2,#1
337 cbz x2,1f
339 1:
379 ld1 {v8.4s,v9.4s},[x5]
393 dup v20.4s,v0.s[1]
401 dup v21.4s,v1.s[1]
[all …]
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DARMTargetParserCommon.cpp31 .Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a") in getArchSynonym()
32 .Case("v8.1a", "v8.1-a") in getArchSynonym()
33 .Case("v8.2a", "v8.2-a") in getArchSynonym()
34 .Case("v8.3a", "v8.3-a") in getArchSynonym()
35 .Case("v8.4a", "v8.4-a") in getArchSynonym()
36 .Case("v8.5a", "v8.5-a") in getArchSynonym()
37 .Case("v8.6a", "v8.6-a") in getArchSynonym()
38 .Case("v8.7a", "v8.7-a") in getArchSynonym()
39 .Case("v8.8a", "v8.8-a") in getArchSynonym()
40 .Case("v8.9a", "v8.9-a") in getArchSynonym()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dnvidia,tegra20-sdhci.txt51 - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
52 configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
55 pinctrl-1.
56 - pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
59 using pads at 3V3 and 1V8 levels.
60 - nvidia,only-1-8-v : The presence of this property indicates that the
65 - nvidia,pad-autocal-pull-up-offset-1v8,
66 nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
72 - nvidia,pad-autocal-pull-up-offset-1v8-timeout,
73 nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
[all …]
H A Dnvidia,tegra20-sdhci.yaml43 maxItems: 1
46 maxItems: 1
53 minItems: 1
57 minItems: 1
70 maxItems: 1
83 maxItems: 1
112 nvidia,pad-autocal-pull-down-offset-1v8:
117 nvidia,pad-autocal-pull-down-offset-1v8-timeout:
140 nvidia,pad-autocal-pull-up-offset-1v8:
145 nvidia,pad-autocal-pull-up-offset-1v8-timeout:
[all …]
/freebsd/crypto/openssl/crypto/sm3/asm/
H A Dsm3-riscv64-zvksh.pl20 # 1. Redistributions of source code must retain the above copyright
68 $V8, $V9, $V10, $V11, $V12, $V13, $V14, $V15,
94 @{[vle32_v $V8, $INPUT]} # v8 := {w15, ..., w8}
97 addi $NUM, $NUM, -1
105 @{[vsm3c_vi $V0, $V4, 1]}
109 @{[vslideup_vi $V4, $V8, 4]} # v4 := {w11, w10, w9, w8, w7, w6, w5, w4}
115 @{[vsm3c_vi $V0, $V8, 4]}
116 @{[vslidedown_vi $V4, $V8, 2]} # v4 := {X, X, w15, w14, w13, w12, w11, w10}
119 @{[vsm3me_vv $V6, $V8, $V6]} # v6 := {w23, w22, w21, w20, w19, w18, w17, w16}
133 @{[vsm3me_vv $V8, $V6, $V8]} # v8 := {w31, w30, w29, w28, w27, w26, w25, w24}
[all …]
/freebsd/sys/netgraph/
H A Dng_patch.c11 * 1. Redistributions of source code must retain the above copyright
239 case 1: in ng_patch_rcvmsg()
240 conf->ops[i].val.v8 = conf->ops[i].val.v1; in ng_patch_rcvmsg()
243 conf->ops[i].val.v8 = conf->ops[i].val.v2; in ng_patch_rcvmsg()
246 conf->ops[i].val.v8 = conf->ops[i].val.v4; in ng_patch_rcvmsg()
265 case 1: in ng_patch_rcvmsg()
266 conf->ops[i].val.v1 = (uint8_t) conf->ops[i].val.v8; in ng_patch_rcvmsg()
269 conf->ops[i].val.v2 = (uint16_t) conf->ops[i].val.v8; in ng_patch_rcvmsg()
272 conf->ops[i].val.v4 = (uint32_t) conf->ops[i].val.v8; in ng_patch_rcvmsg()
368 case 1: in do_patch()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,coresight-cti.yaml31 are implementation defined, except when the CTI is connected to an ARM v8
34 In this case the ARM v8 architecture defines the required signal connections
35 between CTI and the CPU core and ETM if present. In the case of a v8
37 indicate this feature (arm,coresight-cti-v8-arch).
87 - const: arm,coresight-cti-v8-arch
92 maxItems: 1
99 maxItems: 1
114 arm,coresight-cti-v8-arch used. If the associated device has not been
125 const: 1
141 maxItems: 1
[all...]
H A Dcoresight-cti.yaml32 are implementation defined, except when the CTI is connected to an ARM v8
35 In this case the ARM v8 architecture defines the required signal connections
36 between CTI and the CPU core and ETM if present. In the case of a v8
38 indicate this feature (arm,coresight-cti-v8-arch).
88 - const: arm,coresight-cti-v8-arch
93 maxItems: 1
99 base cti node if compatible string arm,coresight-cti-v8-arch is used,
115 compatible string arm,coresight-cti-v8-arch used. If the associated
126 const: 1
140 maxItems: 1
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.td37 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
150 // True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
153 "Has v8 acquire/release (lda/ldaex "
379 "Model MVE instructions as a 1 beat per tick architecture">;
384 def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "1",
398 /// Disable +1 predication cost for instructions updating CPSR.
400 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
404 "Disable +1 predication cost for instructions updating CPSR">;
481 /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
507 "Enable v8.5a Speculation Barrier" >;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp103 Cost += 1; in getRISCVInstructionCost()
146 if (!isa<ConstantInt>(BO->getOperand(1))) in canUseShiftPair()
149 unsigned ShAmt = cast<ConstantInt>(BO->getOperand(1))->getZExtValue(); in canUseShiftPair()
188 if (Idx == 1 || !Inst) in getIntImmCostInst()
214 if (Inst && Idx == 1 && Imm.getBitWidth() <= ST->getXLen() && in getIntImmCostInst()
234 if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2()) in getIntImmCostInst()
244 ImmArgIdx = 1; in getIntImmCostInst()
319 llvm::bit_floor(std::clamp<unsigned>(RVVRegisterWidthLMUL, 1, 8)); in getRegisterBitWidth()
382 // vwaddu.vv v10, v8, v9 in getShuffleCost()
383 // li a0, -1 (ignored) in getShuffleCost()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dfixed-regulator.yaml61 maxItems: 1
64 maxItems: 1
71 maxItems: 1
78 maxItems: 1
87 maxItems: 1
111 maxItems: 1
125 reg_1v8: regulator-1v8 {
127 regulator-name = "1v8";
137 reg_1v8_clk: regulator-1v8-clk {
139 regulator-name = "1v8";
[all …]
/freebsd/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600p8-ppc.pl49 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
66 # v0 A[0][0] A[1][0]
67 # v1 A[0][1] A[1][1]
68 # v2 A[0][2] A[1][2]
69 # v3 A[0][3] A[1][3]
70 # v4 A[0][4] A[1][4]
73 # v6 A[2][1] A[3][1]
75 # v8 A[2][3] A[3][3]
78 # v10 A[4][0] A[4][1]
100 vxor v26,v0, v5 ; A[0..1][0]^A[2..3][0]
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi6220-coresight.dtsi78 #address-cells = <1>;
89 port@1 {
90 reg = <1>;
147 #address-cells = <1>;
158 port@1 {
159 reg = <1>;
380 compatible = "arm,coresight-cti-v8-arch",
391 /* CTI - CPU-1 */
393 compatible = "arm,coresight-cti-v8-arch",
406 compatible = "arm,coresight-cti-v8-arch",
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DAArch64TargetParser.h81 Features.split(Feats, ',', -1, false); // discard empty strings in getImpliedFeatures()
102 // Information about a specific architecture, e.g. V8.1-A
106 StringRef Name; // Name as supplied to -march e.g. "armv8.1-a"
121 // v9.5a > v9.4a > v9.3a > v9.2a > v9.1a > v9a;
123 // v8.9a > v8.8a > v8.7a > v8.6a > v8.5a > v8.4a > ... > v8a;
150 StringRef getSubArch() const { return ArchFeature.substr(1); } in getSubArch()
279 // themselves, they are sequential (0, 1, 2, 3, ...).
/freebsd/crypto/openssh/regress/unittests/sshbuf/
H A Dtest_sshbuf_getput_basic.c35 u_char v8; in sshbuf_getput_basic_tests() local
84 ASSERT_U8_EQ(cd[1], 0x22); in sshbuf_getput_basic_tests()
93 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
100 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
108 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
167 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
171 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
174 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
183 ASSERT_INT_EQ(sshbuf_get_u8(p1, &v8), 0); in sshbuf_getput_basic_tests()
184 ASSERT_U8_EQ(v8, 0x11); in sshbuf_getput_basic_tests()
[all …]

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