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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DARMTargetParserCommon.cpp31 .Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a") in getArchSynonym()
32 .Case("v8.1a", "v8.1-a") in getArchSynonym()
33 .Case("v8.2a", "v8.2-a") in getArchSynonym()
34 .Case("v8.3a", "v8.3-a") in getArchSynonym()
35 .Case("v8.4a", "v8.4-a") in getArchSynonym()
36 .Case("v8.5a", "v8.5-a") in getArchSynonym()
37 .Case("v8.6a", "v8.6-a") in getArchSynonym()
38 .Case("v8.7a", "v8.7-a") in getArchSynonym()
39 .Case("v8.8a", "v8.8-a") in getArchSynonym()
40 .Case("v8.9a", "v8.9-a") in getArchSynonym()
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dnvidia,tegra20-sdhci.txt51 - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
52 configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
55 pinctrl-1.
56 - pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
59 using pads at 3V3 and 1V8 levels.
60 - nvidia,only-1-8-v : The presence of this property indicates that the
65 - nvidia,pad-autocal-pull-up-offset-1v8,
66 nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
72 - nvidia,pad-autocal-pull-up-offset-1v8-timeout,
73 nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
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H A Dnvidia,tegra20-sdhci.yaml43 maxItems: 1
46 maxItems: 1
53 minItems: 1
57 minItems: 1
70 maxItems: 1
83 maxItems: 1
112 nvidia,pad-autocal-pull-down-offset-1v8:
117 nvidia,pad-autocal-pull-down-offset-1v8-timeout:
140 nvidia,pad-autocal-pull-up-offset-1v8:
145 nvidia,pad-autocal-pull-up-offset-1v8-timeout:
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/freebsd/sys/netgraph/
H A Dng_patch.c11 * 1. Redistributions of source code must retain the above copyright
239 case 1: in ng_patch_rcvmsg()
240 conf->ops[i].val.v8 = conf->ops[i].val.v1; in ng_patch_rcvmsg()
243 conf->ops[i].val.v8 = conf->ops[i].val.v2; in ng_patch_rcvmsg()
246 conf->ops[i].val.v8 = conf->ops[i].val.v4; in ng_patch_rcvmsg()
265 case 1: in ng_patch_rcvmsg()
266 conf->ops[i].val.v1 = (uint8_t) conf->ops[i].val.v8; in ng_patch_rcvmsg()
269 conf->ops[i].val.v2 = (uint16_t) conf->ops[i].val.v8; in ng_patch_rcvmsg()
272 conf->ops[i].val.v4 = (uint32_t) conf->ops[i].val.v8; in ng_patch_rcvmsg()
368 case 1: in do_patch()
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/freebsd/sys/crypto/openssl/aarch64/
H A Daes-gcm-armv8_64.S41 sub x5, x5, #1 //byte_len - 1
48 fmov d1, x10 //CTR block 1
51 add w12, w12, #1 //increment rev_ctr32
55 rev w9, w12 //CTR block 1
56 add w12, w12, #1 //CTR block 1
59 orr x9, x11, x9, lsl #32 //CTR block 1
62 fmov v1.d[1], x9 //CTR block 1
67 add w12, w12, #1 //CTR block 2
69 fmov v2.d[1], x9 //CTR block 2
75 add w12, w12, #1 //CTR block 3
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H A Dvpaes-armv8.S163 and x11, x11, #~(1<<6) // and $0x30, %r11 # ... mod 4
165 sub w8, w8, #1 // nr--
170 ushr v0.16b, v0.16b, #4 // vpsrlb $4, %xmm0, %xmm0 # 1 = i
173 tbl v3.16b, {v18.16b}, v0.16b // vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i
174 tbl v4.16b, {v18.16b}, v1.16b // vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j
175 eor v3.16b, v3.16b, v5.16b // vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k
176 eor v4.16b, v4.16b, v5.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k
177 tbl v2.16b, {v18.16b}, v3.16b // vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak
178 tbl v3.16b, {v18.16b}, v4.16b // vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak
226 ushr v8.16b, v15.16b, #4
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H A Darmv8-mont.S42 ldp x7,x8,[x1],#16 // ap[0..1]
46 ldp x13,x14,[x3],#16 // np[0..1]
51 mul x10,x8,x9 // ap[1]*bp[0]
59 mul x16,x14,x15 // np[1]*m1
69 // by adding -1 to x6. That's what next instruction does.
70 subs xzr,x6,#1 // (*)
91 str x12,[x22],#8 // tp[j-1]
104 sub x20,x5,#8 // i=num-1
120 mul x10,x8,x9 // ap[1]*bp[i]
130 mul x16,x14,x15 // np[1]*m1
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H A Dchacha-armv8.S14 .long 1,2,3,4
82 sub x4,x4,#1
233 add x28,x28,#1 // increment counter
256 sub x0,x0,#1
288 add x2,x2,#1
339 ld1 {v8.4s,v9.4s},[x5]
353 dup v20.4s,v0.s[1]
361 dup v21.4s,v1.s[1]
369 dup v23.4s,v3.s[1]
375 add v19.4s,v19.4s,v8.4s
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H A Dpoly1305-armv8.S58 mov x0,#1
214 str w13,[x0,#16*1] // r1
356 mov x4,x7 // r^1
381 mov x4,#1
440 ldp x8,x12,[x1],#16 // inp[0:1]
445 ld1 {v8.4s},[x15]
472 movi v31.2d,#-1
484 // ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^3+inp[7]*r
487 // ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^4+inp[7]*r^2+inp[9])*r
523 umlal v19.2d,v15.2s,v8.s[2]
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/freebsd/crypto/openssl/crypto/aes/asm/
H A Dvpaes-armv8.pl46 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
226 and x11, x11, #~(1<<6) // and \$0x30, %r11 # ... mod 4
228 sub w8, w8, #1 // nr--
233 ushr v0.16b, v0.16b, #4 // vpsrlb \$4, %xmm0, %xmm0 # 1 = i
236 tbl v3.16b, {$invlo}, v0.16b // vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i
237 tbl v4.16b, {$invlo}, v1.16b // vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j
238 eor v3.16b, v3.16b, v5.16b // vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k
239 eor v4.16b, v4.16b, v5.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k
240 tbl v2.16b, {$invlo}, v3.16b // vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak
241 tbl v3.16b, {$invlo}, v4.16b // vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,coresight-cti.yaml31 are implementation defined, except when the CTI is connected to an ARM v8
34 In this case the ARM v8 architecture defines the required signal connections
35 between CTI and the CPU core and ETM if present. In the case of a v8
37 indicate this feature (arm,coresight-cti-v8-arch).
87 - const: arm,coresight-cti-v8-arch
92 maxItems: 1
99 maxItems: 1
114 arm,coresight-cti-v8-arch used. If the associated device has not been
125 const: 1
141 maxItems: 1
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H A Dcoresight-cti.yaml32 are implementation defined, except when the CTI is connected to an ARM v8
35 In this case the ARM v8 architecture defines the required signal connections
36 between CTI and the CPU core and ETM if present. In the case of a v8
38 indicate this feature (arm,coresight-cti-v8-arch).
88 - const: arm,coresight-cti-v8-arch
93 maxItems: 1
99 base cti node if compatible string arm,coresight-cti-v8-arch is used,
115 compatible string arm,coresight-cti-v8-arch used. If the associated
126 const: 1
140 maxItems: 1
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.td37 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
150 // True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
153 "Has v8 acquire/release (lda/ldaex "
379 "Model MVE instructions as a 1 beat per tick architecture">;
384 def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "1",
398 /// Disable +1 predication cost for instructions updating CPSR.
400 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
404 "Disable +1 predication cost for instructions updating CPSR">;
481 /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
507 "Enable v8.5a Speculation Barrier" >;
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp103 Cost += 1; in getRISCVInstructionCost()
146 if (!isa<ConstantInt>(BO->getOperand(1))) in canUseShiftPair()
149 unsigned ShAmt = cast<ConstantInt>(BO->getOperand(1))->getZExtValue(); in canUseShiftPair()
188 if (Idx == 1 || !Inst) in getIntImmCostInst()
214 if (Inst && Idx == 1 && Imm.getBitWidth() <= ST->getXLen() && in getIntImmCostInst()
234 if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2()) in getIntImmCostInst()
244 ImmArgIdx = 1; in getIntImmCostInst()
319 llvm::bit_floor(std::clamp<unsigned>(RVVRegisterWidthLMUL, 1, 8)); in getRegisterBitWidth()
382 // vwaddu.vv v10, v8, v9 in getShuffleCost()
383 // li a0, -1 (ignored) in getShuffleCost()
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dfixed-regulator.yaml61 maxItems: 1
64 maxItems: 1
71 maxItems: 1
78 maxItems: 1
87 maxItems: 1
111 maxItems: 1
125 reg_1v8: regulator-1v8 {
127 regulator-name = "1v8";
137 reg_1v8_clk: regulator-1v8-clk {
139 regulator-name = "1v8";
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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600p8-ppc.pl49 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
66 # v0 A[0][0] A[1][0]
67 # v1 A[0][1] A[1][1]
68 # v2 A[0][2] A[1][2]
69 # v3 A[0][3] A[1][3]
70 # v4 A[0][4] A[1][4]
73 # v6 A[2][1] A[3][1]
75 # v8 A[2][3] A[3][3]
78 # v10 A[4][0] A[4][1]
100 vxor v26,v0, v5 ; A[0..1][0]^A[2..3][0]
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi6220-coresight.dtsi78 #address-cells = <1>;
89 port@1 {
90 reg = <1>;
147 #address-cells = <1>;
158 port@1 {
159 reg = <1>;
380 compatible = "arm,coresight-cti-v8-arch",
391 /* CTI - CPU-1 */
393 compatible = "arm,coresight-cti-v8-arch",
406 compatible = "arm,coresight-cti-v8-arch",
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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DAArch64TargetParser.h81 Features.split(Feats, ',', -1, false); // discard empty strings in getImpliedFeatures()
102 // Information about a specific architecture, e.g. V8.1-A
106 StringRef Name; // Name as supplied to -march e.g. "armv8.1-a"
121 // v9.5a > v9.4a > v9.3a > v9.2a > v9.1a > v9a;
123 // v8.9a > v8.8a > v8.7a > v8.6a > v8.5a > v8.4a > ... > v8a;
150 StringRef getSubArch() const { return ArchFeature.substr(1); } in getSubArch()
279 // themselves, they are sequential (0, 1, 2, 3, ...).
/freebsd/crypto/openssh/regress/unittests/sshbuf/
H A Dtest_sshbuf_getput_basic.c35 u_char v8; in sshbuf_getput_basic_tests() local
84 ASSERT_U8_EQ(cd[1], 0x22); in sshbuf_getput_basic_tests()
93 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
100 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
108 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
167 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
171 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
174 ASSERT_SIZE_T_EQ(sshbuf_len(p1), 1); in sshbuf_getput_basic_tests()
183 ASSERT_INT_EQ(sshbuf_get_u8(p1, &v8), 0); in sshbuf_getput_basic_tests()
184 ASSERT_U8_EQ(v8, 0x11); in sshbuf_getput_basic_tests()
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/freebsd/sys/arm/arm/
H A Dstdatomic.c10 * 1. Redistributions of source code must retain the above copyright
113 uint8_t v8[4]; member
141 r->v8[offset] = val; in put_1()
150 return (r->v8[offset]); in get_1()
164 r->v8[offset] = bytes.out[0]; in put_2()
165 r->v8[offset + 1] = bytes.out[1]; in put_2()
178 bytes.in[0] = r->v8[offset]; in get_2()
179 bytes.in[1] = r->v8[offset + 1]; in get_2()
206 "1:" \
210 "\tstrex %3, %2, %1\n" /* Attempt to store. */ \
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SystemOperands.td25 "ARM v8.1 Privileged Access-Never extension">;
29 "ARM v8.2 UAO PState extension (psuao)">;
33 "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">;
76 // v8.9a/v9.4a FEAT_ATS1A
200 def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>;
240 string policy, bits<1> policy_encoding> : SearchableTable {
247 let Encoding{2-1} = target_encoding;
317 class RPRFM<string name, bits<1> type_encoding, bits<5> policy_encoding> : SearchableTable {
324 let Encoding{5-1} = policy_encoding;
368 class SVEVECLENSPECIFIER<string name, bits<1> encoding> : SearchableTable {
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H A DAArch64Features.td105 // Armv8.1 Architecture Extensions
109 "Enable Armv8.1-A Large System Extension (LSE) atomic instructions">;
113 "Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions",
117 "Enable Armv8.1-A Privileged Access-Never extension">;
120 "Enable Armv8.1-A Limited Ordering Regions extension">;
126 "Enable Armv8.1-A Virtual Host extension", [FeatureCONTEXTIDREL2]>;
189 "Enable v8.3-A Pointer Authentication Faulting enhancement">;
396 // Armv9.1 Architecture Extensions
439 "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions", [FeatureBF16]>;
448 "Enable SME2.1 ZA-targeting non-widening BFloat16 instructions", [FeatureSME2, FeatureB16B16]>;
[all …]
/freebsd/tests/sys/cddl/zfs/tests/cli_root/zpool_import/
H A Dzpool_import.cfg45 for (( num=0 ; $num < $GROUP_NUM ; num += 1 )); do
51 for (( num = GROUP_NUM ; $num < $MAX_NUM ; num += 1 )); do
61 # Version 1 pools
81 # This is a v8 pool
82 export ZPOOL_VERSION_8_FILES="zfs-pool-v8.dat"
83 export ZPOOL_VERSION_8_NAME="v8-pool"
99 # we should be able to upgrade pools of version 1, 2 & 3
/freebsd/sys/contrib/openzfs/include/os/freebsd/spl/sys/
H A Disa_defs.h197 #define _SUNOS_VTOC_16 1
203 * architectures. This includes SPARC V7, SPARC V8 and SPARC V9.
205 * The symbol __sparcv8 indicates the 32-bit SPARC V8 architecture as defined
207 * to SPARC V8 for the former to be subsumed into the latter definition.)
235 * if you haven't asked for SPARC V9, then you must've meant SPARC V8.
248 * 32-bit Solaris on SPARC V8 systems.
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td48 let Entry = 1 in
70 let Entry = 1 in
96 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
102 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
121 let Entry = 1 in
143 CCIfNotVarArg<CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,
152 CCIfNotVarArg<CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,
159 let Entry = 1 in
175 let Entry = 1 in
189 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
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