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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMips32r6InstrFormats.td121 let Inst{31-26} = 0b000000;
229 let Inst{31-26} = 0b000000;
307 let Inst{31-26} = 0b000000;
320 let Inst{31-26} = 0b000000;
336 let Inst{31-26} = 0b000000;
366 let Inst{31-26} = 0b000000;
681 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
707 let Inst{3-1} = rd;
748 let Inst{1-0} = rs{1-0};
782 let Inst{3-1} = rd;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,ipesys.txt10 - #clock-cells: Must be 1
18 ipesys: clock-controller@1b000000 {
21 #clock-cells = <1>;
H A Dmediatek,ethsys.txt15 - #clock-cells: Must be 1
16 - #reset-cells: Must be 1
24 ethsys: clock-controller@1b000000 {
27 #clock-cells = <1>;
28 #reset-cells = <1>;
H A Dmediatek,mt8192-clock.yaml41 maxItems: 1
44 const: 1
57 #clock-cells = <1>;
64 #clock-cells = <1>;
71 #clock-cells = <1>;
78 #clock-cells = <1>;
85 #clock-cells = <1>;
92 #clock-cells = <1>;
99 #clock-cells = <1>;
106 #clock-cells = <1>;
[all …]
H A Dmediatek,mt8195-clock.yaml53 maxItems: 1
56 const: 1
69 #clock-cells = <1>;
76 #clock-cells = <1>;
83 #clock-cells = <1>;
90 #clock-cells = <1>;
97 #clock-cells = <1>;
104 #clock-cells = <1>;
111 #clock-cells = <1>;
118 #clock-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Darm,hdlcd.yaml24 maxItems: 1
27 maxItems: 1
33 maxItems: 1
37 maxItems: 1
43 maxItems: 1
62 hdlcd@2b000000 {
77 #address-cells = <1>;
H A Darm,hdlcd.txt36 hdlcd@2b000000 {
68 hdmi1: connector@1 {
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DResourceManager.h32 /// with a buffer size of -1 is always available if it is not reserved.
152 /// A | 0b000001 | 0b000001 | 0b000000
154 /// B | 0b000010 | 0b000010 | 0b000000
156 /// C | 0b010000 | 0b010000 | 0b000000
184 /// A BufferSize of 1 is used by scheduler resources that force in-order
222 bool isInOrder() const { return BufferSize == 1; } in isInOrder()
233 bool isReady(unsigned NumUnits = 1) const;
250 return isAResourceGroup() ? 1U : llvm::popcount(ResourceSizeMask); in getNumUnits()
330 // A | 0b00001 | 0b00001 | 1
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62a-wakeup.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
50 #address-cells = <1>;
68 wkup_rti0: watchdog@2b000000 {
84 #thermal-sensor-cells = <1>;
H A Dk3-am62p-wakeup.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
47 #address-cells = <1>;
65 wkup_rti0: watchdog@2b000000 {
81 #thermal-sensor-cells = <1>;
86 #address-cells = <1>;
87 #size-cells = <1>;
101 resets = <&k3_reset 121 1>;
103 ti,atcm-enable = <1>;
104 ti,btcm-enable = <1>;
[all …]
H A Dk3-am62p-j722s-common-wakeup.dtsi12 #address-cells = <1>;
13 #size-cells = <1>;
53 #address-cells = <1>;
71 wkup_rti0: watchdog@2b000000 {
87 #thermal-sensor-cells = <1>;
92 #address-cells = <1>;
93 #size-cells = <1>;
107 resets = <&k3_reset 121 1>;
109 ti,atcm-enable = <1>;
110 ti,btcm-enable = <1>;
[all …]
H A Dk3-am62-wakeup.dtsi15 #address-cells = <1>;
16 #size-cells = <1>;
54 ti,syss-mask = <1>;
59 #address-cells = <1>;
60 #size-cells = <1>;
75 #address-cells = <1>;
93 wkup_rti0: watchdog@2b000000 {
109 #thermal-sensor-cells = <1>;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmediatek,mt8192-clock.yaml41 maxItems: 1
44 const: 1
57 #clock-cells = <1>;
64 #clock-cells = <1>;
71 #clock-cells = <1>;
78 #clock-cells = <1>;
85 #clock-cells = <1>;
92 #clock-cells = <1>;
99 #clock-cells = <1>;
106 #clock-cells = <1>;
[all …]
H A Dmediatek,mt8195-clock.yaml53 maxItems: 1
56 const: 1
69 #clock-cells = <1>;
76 #clock-cells = <1>;
83 #clock-cells = <1>;
90 #clock-cells = <1>;
97 #clock-cells = <1>;
104 #clock-cells = <1>;
111 #clock-cells = <1>;
118 #clock-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqcs8550.dtsi18 * 1. Firmware related regions which aren't shared with kernel.
92 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
H A Dipq5018.dtsi31 #address-cells = <1>;
44 CPU1: cpu@1 {
133 #address-cells = <1>;
134 #size-cells = <1>;
180 #clock-cells = <1>;
181 #reset-cells = <1>;
187 #hwlock-cells = <1>;
213 #dma-cells = <1>;
229 #address-cells = <1>;
260 #address-cells = <1>;
[all …]
H A Dipq5332.dtsi31 #address-cells = <1>;
44 CPU1: cpu@1 {
153 #address-cells = <1>;
154 #size-cells = <1>;
173 #address-cells = <1>;
174 #size-cells = <1>;
176 cpu_speed_bin: cpu-speed-bin@1d {
210 #clock-cells = <1>;
211 #reset-cells = <1>;
212 #interconnect-cells = <1>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td39 def SDT_BITCAST_TO_LOHI : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
41 def SDT_BITCAST_FROM_LOHI : SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>]>;
108 def FADDM : F_XYZ<0x2, 0b000000, "faddm", "", BinOpFrag<(fadd node:$LHS, node:$RHS)>, sFPR64_V_OP>;
123 defm FADD : FT_XYZ<0b000000, "fadd", BinOpFrag<(fadd node:$LHS, node:$RHS)>>;
162 let isCodeGenOnly = 1 in
167 let isCodeGenOnly = 1 in
206 def rnFSTOSI : F_XZ_TRANS<0b000000, "fstosi.rn", sFPR32Op, sFPR32Op>;
260 let hasSideEffects = 0, mayLoad = 1, mayStor
[all...]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15-tc1.dts5 * CoreTile Express A15x2 (version with Test Chip 1)
35 #address-cells = <1>;
44 cpu@1 {
47 reg = <1>;
70 hdlcd@2b000000 {
103 interrupts = <1 9 0xf04>;
129 interrupts = <1 13 0xf08>,
130 <1 14 0xf08>,
131 <1 11 0xf08>,
132 <1 10 0xf08>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,pru-rproc.yaml21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
70 maxItems: 1
121 #address-cells = <1>;
122 #size-cells = <1>;
128 #address-cells = <1>;
129 #size-cells = <1>;
163 icssg0: icssg@b000000 {
167 #address-cells = <1>;
168 #size-cells = <1>;
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6779.dtsi25 #address-cells = <1>;
35 cpu1: cpu@1 {
134 ppi_cluster1: interrupt-partition-1 {
153 #clock-cells = <1>;
159 #clock-cells = <1>;
189 #clock-cells = <1>;
242 #clock-cells = <1>;
248 #clock-cells = <1>;
254 #clock-cells = <1>;
260 #clock-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-conn.dtsi38 conn_subsys: bus@5b000000 {
40 #address-cells = <1>;
41 #size-cells = <1>;
60 #index-cells = <1>;
151 #address-cells = <1>;
152 #size-cells = <1>;
198 #clock-cells = <1>;
212 #clock-cells = <1>;
226 #clock-cells = <1>;
240 #clock-cells = <1>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td63 let Inst{31} = 1;
64 let Inst{30} = 1;
96 let Inst{31} = 1;
97 let Inst{30-25} = 0b000000;
/freebsd/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini.dtsi13 #address-cells = <1>;
14 #size-cells = <1>;
32 #clock-cells = <1>;
33 #reset-cells = <1>;
181 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
218 pinctrl-1 = <&sata_and_ide_pins>;
231 power-controller@4b000000 {
292 #interrupt-cells = <1>;
295 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
296 <0x4800 0 0 2 &pci_intc 1>,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td29 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
38 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
43 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
51 def SDT_XCoreAddress : SDTypeProfile<1, 1,
52 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
66 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
70 def SDT_XCoreLdwsp : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
76 SDTCisVT<1, i32> ]>;
78 SDTCisVT<1, i32> ]>;
141 return (uint32_t)N->getZExtValue() < (1 << 6);
[all …]

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