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/linux/tools/testing/selftests/powerpc/math/
H A Dvmx_asm.S9 # Should be safe from C, only touches r4, r5 and v0,v1,v2
13 li r3,1 # assume a bad result
17 vmr v2,v1
22 vand v2,v2,v1
27 vand v2,v2,v1
32 vand v2,v2,v1
37 vand v2,v2,v1
42 vand v2,v2,v1
47 vand v2,v2,v1
52 vand v2,v2,v1
[all …]
/linux/net/ceph/
H A Dmessenger_v2.c30 #define FRAME_TAG_HELLO 1
55 #define IN_S_HANDLE_PREAMBLE 1
66 #define OUT_S_QUEUE_DATA 1
98 return 1; in do_recvmsg()
105 * 1 - done, nothing (else) to read
114 iov_iter_is_discard(&con->v2.in_iter) ? "discard" : "need", in ceph_tcp_recv()
115 iov_iter_count(&con->v2.in_iter)); in ceph_tcp_recv()
116 ret = do_recvmsg(con->sock, &con->v2.in_iter); in ceph_tcp_recv()
118 iov_iter_count(&con->v2.in_iter)); in ceph_tcp_recv()
140 return 1; in do_sendmsg()
[all …]
/linux/arch/s390/include/asm/
H A Dfpu-insn.h108 "1: nopr %%r7\n" in fpu_lfpc_safe()
112 " jg 1b\n" in fpu_lfpc_safe()
114 EX_TABLE(1b, 2b) in fpu_lfpc_safe()
146 static __always_inline void fpu_vab(u8 v1, u8 v2, u8 v3) in fpu_vab() argument
148 asm volatile("VAB %[v1],%[v2],%[v3]" in fpu_vab()
150 : [v1] "I" (v1), [v2] "I" (v2), [v3] "I" (v3) in fpu_vab()
154 static __always_inline void fpu_vcksm(u8 v1, u8 v2, u8 v3) in fpu_vcksm() argument
156 asm volatile("VCKSM %[v1],%[v2],%[v3]" in fpu_vcksm()
158 : [v1] "I" (v1), [v2] "I" (v2), [v3] "I" (v3) in fpu_vcksm()
162 static __always_inline void fpu_vesravb(u8 v1, u8 v2, u8 v3) in fpu_vesravb() argument
[all …]
H A Dfpu-insn-asm.h34 \opd = 1
98 \opd = 1
100 .ifc \vxr,%v2
201 * @v2: Vector register designated operand whose MSB is stored in
202 * RXB bit 1 (instruction bit 37) and whose remaining bits
211 * Note: In most vector instruction formats [1] V1, V2, V3, and V4 directly
212 * correspond to @v1, @v2, @v3, and @v4. But there are exceptions, such as but
216 * [1] IBM z/Architecture Principles of Operation, chapter "Program
219 .macro RXB rxb v1 v2=0 v3=0 v4=0
224 .if \v2 & 0x10
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
39 operating-points-v2 = <&cpu0_opp_table0>;
42 cpu@1 {
45 reg = <1>;
50 operating-points-v2 = <&cpu0_opp_table0>;
55 compatible = "operating-points-v2";
[all …]
/linux/include/uapi/linux/
H A Dnfs.h22 #define NFS_FIFO_DEV (-1)
33 #define NFS_MNT_VERSION 1
43 * Error codes that have a `--' in the v2 column are not part of the
47 NFS_OK = 0, /* v2 v3 v4 */
48 NFSERR_PERM = 1, /* v2 v3 v4 */
49 NFSERR_NOENT = 2, /* v2 v3 v4 */
50 NFSERR_IO = 5, /* v2 v3 v4 */
51 NFSERR_NXIO = 6, /* v2 v3 v4 */
52 NFSERR_EAGAIN = 11, /* v2 v3 */
53 NFSERR_ACCES = 13, /* v2 v3 v4 */
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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,saw2.yaml31 - qcom,sdm660-gold-saw2-v4.1-l2
32 - qcom,sdm660-silver-saw2-v4.1-l2
33 - qcom,msm8998-gold-saw2-v4.1-l2
34 - qcom,msm8998-silver-saw2-v4.1-l2
38 - qcom,msm8226-saw2-v2.1-cpu
39 - qcom,msm8226-saw2-v2.1-l2
41 - qcom,msm8974-saw2-v2.1-cpu
42 - qcom,msm8974-saw2-v2.1-l2
43 - qcom,msm8976-gold-saw2-v2.3-l2
44 - qcom,msm8976-silver-saw2-v2.3-l2
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml15 Management Unit Architecture, which can be used to provide 1 or 2 stages
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
116 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
119 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2
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/linux/arch/arm64/crypto/
H A Dsm4-ce-core.S17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
63 sm4ekey v2.4s, v1.4s, v26.4s;
64 sm4ekey v3.4s, v2.4s, v27.4s;
81 tbl v21.16b, {v2.16b}, v24.16b
124 SM4_CRYPT_BLK8(v0, v1, v2, v3, v4, v5, v6, v7);
140 SM4_CRYPT_BLK4(v0, v1, v2, v3);
146 sub w3, w3, #1;
183 eor v2.16b, v2.16b, v1.16b
184 SM4_CRYPT_BLK(v2)
185 eor v3.16b, v3.16b, v2.16b
[all …]
H A Daes-ce-ccm-core.S37 tbz \nr, #1, .L\@
57 add x8, x8, #1
59 ins v1.d[1], x9 /* no carry in lower ctr */
65 ld1 {v2.16b}, [x1], #16 /* load next input block */
66 .if \enc == 1
67 eor v2.16b, v2.16b, v5.16b /* final round enc+mac */
68 eor v6.16b, v1.16b, v2.16b /* xor with crypted ctr */
70 eor v2.16b, v2.16b, v1.16b /* xor with crypted ctr */
71 eor v6.16b, v2.16b, v5.16b /* final round enc */
73 eor v0.16b, v0.16b, v2.16b /* xor mac with pt ^ rk[last] */
[all …]
H A Daes-modes.S26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
76 subs w4, w4, #1
106 subs w4, w4, #1
148 eor v2.16b, v2.16b, v1.16b
149 encrypt_block v2, w3, x2, x6, w7
150 eor v3.16b, v3.16b, v2.16b
163 subs w4, w4, #1
[all …]
H A Dsm3-ce-core.S12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
46 shl \t1\().4s, \t0\().4s, #1
63 round \ab, \s0, v12, v11, 1
90 sub w2, w2, #1
97 CPU_LE( rev32 v2.16b, v2.16b )
102 qround a, v0, v1, v2, v3, v4
103 qround a, v1, v2, v3, v4, v0
104 qround a, v2, v3, v4, v0, v1
105 qround a, v3, v4, v0, v1, v2
109 qround b, v4, v0, v1, v2, v3
[all …]
H A Daes-ce-core.S20 0: mov v2.16b, v1.16b
22 1: aese v0.16b, v2.16b
27 3: ld1 {v2.4s}, [x0], #16
32 bpl 1b
33 aese v0.16b, v2.16b
48 0: mov v2.16b, v1.16b
50 1: aesd v0.16b, v2.16b
55 3: ld1 {v2.4s}, [x0], #16
60 bpl 1b
61 aesd v0.16b, v2.16b
/linux/arch/powerpc/lib/
H A Dxor_vmx.c31 V##_1 = V[1]; \
39 V[1] = V##_1; \
44 #define XOR(V1, V2) \ argument
46 V1##_0 = vec_xor(V1##_0, V2##_0); \
47 V1##_1 = vec_xor(V1##_1, V2##_1); \
48 V1##_2 = vec_xor(V1##_2, V2##_2); \
49 V1##_3 = vec_xor(V1##_3, V2##_3); \
57 DEFINE(v2); in __xor_altivec_2()
62 LOAD(v2); in __xor_altivec_2()
63 XOR(v1, v2); in __xor_altivec_2()
[all …]
/linux/Documentation/arch/powerpc/
H A Disa-versions.rst12 Power10 Power ISA v3.1
14 Power8 Power ISA v2.07
15 e6500 Power ISA v2.06 with some exceptions
16 e5500 Power ISA v2.06 with some exceptions, no Altivec
17 Power7 Power ISA v2.06
18 Power6 Power ISA v2.05
19 PA6T Power ISA v2.04
20 Cell PPU - Power ISA v2.02 with some minor exceptions
22 Power5++ Power ISA v2.04 (no VMX)
23 Power5+ Power ISA v2.03
[all …]
/linux/drivers/char/mwave/
H A Dmwavedd.h84 #define PRINTK_3(f,s,v1,v2) \ argument
86 printk(s,v1,v2); \
89 #define PRINTK_4(f,s,v1,v2,v3) \ argument
91 printk(s,v1,v2,v3); \
94 #define PRINTK_5(f,s,v1,v2,v3,v4) \ argument
96 printk(s,v1,v2,v3,v4); \
99 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ argument
101 printk(s,v1,v2,v3,v4,v5); \
104 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ argument
106 printk(s,v1,v2,v3,v4,v5,v6); \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h64 REG_SET_N(reg_name, 1, initial_val, \
67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument
70 FN(reg, f2), v2)
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
75 FN(reg, f2), v2,\
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
81 FN(reg, f2), v2,\
85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
89 FN(reg, f2), v2,\
94 #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm660.dtsi14 operating-points-v2 = <&gpu_sdm660_opp_table>;
17 compatible = "operating-points-v2";
91 /delete-property/ operating-points-v2;
97 /delete-property/ operating-points-v2;
103 /delete-property/ operating-points-v2;
109 /delete-property/ operating-points-v2;
115 /delete-property/ operating-points-v2;
121 /delete-property/ operating-points-v2;
127 /delete-property/ operating-points-v2;
133 /delete-property/ operating-points-v2;
[all …]
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dqcom-cpufreq-nvmem.yaml51 - operating-points-v2-krait-cpu
52 - operating-points-v2-kryo-cpu
54 $ref: /schemas/opp/opp-v2-kryo-cpu.yaml#
59 const: operating-points-v2-qcom-level
61 $ref: /schemas/opp/opp-v2-qcom-level.yaml#
84 maxItems: 1
99 const: operating-points-v2-kryo-cpu
117 #address-cells = <1>;
129 operating-points-v2 = <&cpu_opp_table>;
143 operating-points-v2 = <&cpu_opp_table>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dbrcm,asp-v2.0.yaml4 $id: http://devicetree.org/schemas/net/brcm,asp-v2.0.yaml#
21 - const: brcm,asp-v2.2
25 - const: brcm,asp-v2.1
29 - const: brcm,asp-v2.0
32 const: 1
34 const: 1
37 maxItems: 1
42 minItems: 1
46 - description: Port 1 Wake-on-LAN
49 maxItems: 1
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-3720-db.dts39 gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
72 /* Gigabit module on CON19(V2.0)/CON21(V1.4) */
81 /* Gigabit module on CON18(V2.0)/CON20(V1.4) */
124 phy1: ethernet-phy@1 {
125 reg = <1>;
129 /* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
145 mmc-ddr-1_8v;
146 mmc-hs400-1_8v;
147 marvell,pad-type = "fixed-1-8v";
151 /* SD slot module on CON14(V2.0)/CON15(V1.4) */
[all …]
/linux/Documentation/devicetree/bindings/hwmon/
H A Dltc2990.txt13 0: V1, V2, TR2
14 1: V1-V2, TR2
15 2: V1-V2, V3, V4
19 6: V1-V2, V3-V4
20 7: V1, V2, V3, V4
26 1: TR1, V1 or V1-V2 only per mode
35 lltc,meas-mode = <7 3>; /* V1, V2, V3, V4 */
/linux/drivers/hid/
H A Dhid-uclogic-rdesc.h63 /* Fixed PID 0522 tablet report descriptor, interface 1 (mouse) */
79 /* Fixed TWHA60 report descriptor, interface 1 (frame buttons) */
119 /* Report ID for v2 pen reports */
122 /* Fixed report descriptor template for (tweaked) v2 pen reports */
133 /* Report ID for tweaked v2 frame button reports */
136 /* Fixed report descriptor for (tweaked) v2 frame button reports */
140 /* Report ID for tweaked v2 frame touch ring/strip reports */
143 /* Fixed report descriptor for (tweaked) v2 frame touch ring reports */
147 /* Fixed report descriptor for (tweaked) v2 frame touch strip reports */
151 /* Device ID byte offset in v2 frame touch ring/strip reports */
[all …]
/linux/arch/powerpc/crypto/
H A Dcrc32-vpmsum_core.S101 vspltisw v0,-1
127 1: lis r7,MAX_SIZE@h
148 addi r7,r7,-1
159 vxor v2,v2,v2
172 cmpdi r0,1
268 vxor v2,v2,v10
321 vxor v2,v2,v10
349 vxor v2,v2,v10
365 vsldoi v2,v2,zeroes,4
395 vxor v18,v2,v10
[all …]
/linux/lib/
H A Dxxhash.c56 # define XXH_CPU_LITTLE_ENDIAN 1
111 uint32_t v2 = seed + PRIME32_2; in xxh32() local
118 v2 = xxh32_round(v2, get_unaligned_le32(p)); in xxh32()
126 h32 = xxh_rotl32(v1, 1) + xxh_rotl32(v2, 7) + in xxh32()
181 uint64_t v2 = seed + PRIME64_2; in xxh64() local
188 v2 = xxh64_round(v2, get_unaligned_le64(p)); in xxh64()
196 h64 = xxh_rotl64(v1, 1) + xxh_rotl64(v2, 7) + in xxh64()
199 h64 = xxh64_merge_round(h64, v2); in xxh64()
249 state.v2 = seed + PRIME32_2; in xxh32_reset()
263 state.v2 = seed + PRIME64_2; in xxh64_reset()
[all …]

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